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200 MHz Dual Integrated DCL with Level Setting DACs, Per Pin PMU, and Per Chip VHH ADATE304
FEATURES
Driver 3-level driver with high-Z mode and built-in clamps Precision trimmed output resistance Low leakage mode (typically <10 nA) Voltage range: up to -2.0 V to +6.0 V 2.4 ns minimum pulse width, 2 V terminated Comparator Window and differential comparator 500 MHz input equivalent bandwidth Load 12 mA maximum current capability Per pin PMU Force voltage range: up to -2.0 V to +6.0 V 5 current ranges: 32 mA, 2 mA, 200 A, 20 A, 2 A Levels 14-bit DAC for DCL levels Typically < 5 mV INL (calibrated) 16-bit DAC for PMU levels Typically < 1.5 mV INL (calibrated) linearity in FV mode HVOUT output buffer 0 V to 13.5 V output range 84-lead, 9 mm x 9 mm, CSP_BGA package 900 mW per channel with no load
GENERAL DESCRIPTION
The ADATE304 is a complete, single-chip solution that performs the pin electronic functions of the driver, the comparator, and the active load (DCL), per pin PMU, and dc levels for ATE applications. The device also contains an HVOUT driver with a VHH buffer capable of generating up to 13.5 V. The driver features three active states: data high mode, data low mode, and term mode, as well as an inhibit state. The inhibit state, in conjunction with the integrated dynamic clamp, facilitates the implementation of a high speed active termination. The ADATE304 supports two output voltage ranges: -2.0 V to +6.0 V and -1.25 V to +6.75 V by adjusting the positive and negative supply voltages. Each channel of the ADATE304 features a high speed window comparator per pin for functional testing, as well as a per pin PMU with FV, or FI and MV, or MI functions. All necessary dc levels for DCL functions are generated by on-chip 14-bit DACs. The per pin PMU features an on-chip 16-bit DAC for high accuracy and contains integrated range resistors to minimize external component counts. The ADATE304 uses a serial bus to program all functional blocks and has an on-board temperature sensor for monitoring the device temperature.
APPLICATIONS
Automatic test equipment Semiconductor test systems Board test systems Instrumentation and characterization equipment
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2008 Analog Devices, Inc. All rights reserved.
ADATE304 TABLE OF CONTENTS
Features .............................................................................................. 1 Applications ....................................................................................... 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Functional Block Diagram .............................................................. 3 Specifications..................................................................................... 4 Total Function ............................................................................... 4 Driver ............................................................................................. 5 Reflection Clamp .......................................................................... 7 Normal Window Comparator .................................................... 7 Differential Comparator .............................................................. 9 Active Load.................................................................................. 10 PMU ............................................................................................. 11 External Sense (PMUS_CHx)................................................... 16 DUTGND Input ......................................................................... 16 Serial Peripheral Interface ......................................................... 16 HVOUT Driver ........................................................................... 17 Overvoltage Detector (OVD) ................................................... 18 16-Bit DAC Monitor MUX ....................................................... 18 Absolute Maximum Ratings.......................................................... 19 Thermal Resistance .................................................................... 19 Explanation of Test Levels ......................................................... 19 ESD Caution................................................................................ 19 Pin Configuration and Function Descriptions........................... 20 Typical Performance Characteristics ........................................... 23 SPI Details ....................................................................................... 33 Definition of SPI Word .............................................................. 34 Write Operation.......................................................................... 35 Read Operation........................................................................... 36 Reset Operation .......................................................................... 37 Register Map ................................................................................... 38 Details of Registers ......................................................................... 39 User Information ............................................................................ 41 Power Supply Considerations ................................................... 41 Truth Tables................................................................................. 41 Details of DACs vs. Levels ......................................................... 43 Recommended PMU Mode Switching Sequences................. 45 Block Diagrams............................................................................... 47 Outline Dimensions ....................................................................... 51 Ordering Guide .......................................................................... 51
REVISION HISTORY
10/08--Revision 0: Initial Version
Rev. 0 | Page 2 of 52
ADATE304 FUNCTIONAL BLOCK DIAGRAM
CH1 PMU_FLAG 16-BIT DAC PMU MUX
*
DAC16_MON MUX
VCLAMPH
VCLAMPL
*
MEASOUT01 MUX CH1
OVD
OVD_CH0
PMUS_CH0
FORCE SENSE
VCLAMPH VH VT VL DATA0P 100 DATA0N RCV0P 100 RCV0N COMP_VTT0 COMP_QH0P COMP_QH0N 50 DRV
VCLAMPL
ROUT (TRIMMED) DUT0
*
WINDOW DIFF. C OTHER CHANNEL DUT1 HVOUT
*
VHH
C
VOH
COMP_QL0P COMP_QL0N
C
VOL
*
G IOL
ADATE304
SDIN RST SCLK CS SDOUT
*
SPI 14-BIT DAC
VCOM TEMPERATURE SENSOR
*
TEMPSENSE
IOH
*ONE PER DEVICE.
Figure 1. One of Two Channels
Rev. 0 | Page 3 of 52
07279-001
ADATE304 SPECIFICATIONS
Characterization and production tests performed using Power Supply Range 1 (see Table 37). VDD = +10.75 V, VCC = +3.3 V, VSS = -5.00 V, VPLUS = +16.75 V, VCOMP_VTT = +3.3 V, VREF = +5.0 V, VREF_GND = 0.0 V. All default test conditions are as defined in Table 38. All specified values are at TJ = 55C, where TJ corresponds to the internal temperature sensor and the temperature coefficients are measured at TJ = 55C 20C, unless otherwise noted. Typical values are based on design, simulation analyses, and/or limited bench evaluations. Typical values are not tested or guaranteed. Test levels are specified in the Explanation of Test Levels section.
TOTAL FUNCTION
Table 1.
Parameter TOTAL FUNCTION Output Leakage Current PE Disable Range E PE Disable Range A to Range D Symbol Min Typ Max Unit Test Level Test Conditions/Comments
-20.0
+5.3 5.3
+20.0
nA nA
P CT
High-Z Mode
-400
+5.4
+400
nA
P
Output Capacitance DUT Pin Range POWER SUPPLIES Total Supply Range, VPLUS to VSS VPLUS Supply Positive Supply Negative Supply Logic Supply Comparator Termination VPLUS Supply Current Logic Supply Current Comparator Termination Current Positive Supply Current Negative Supply Current Total Power Dissipation Positive Supply Current Negative Supply Current Total Power Dissipation TEMPERATURE MONITORS Temperature Sensor Gain Temperature Sensor Accuracy Without Calibration over 25C to 100C VREF INPUT Reference Input Voltage Range for DACs (VREF Pin) Input Bias Current
4 -1.25 22.5 16.75 10.75 -5.00 3.3 +1.3 12.7 2.7 17 90.5 116 1.6 120 146 2.2 10 6 +6.0 23.25 17.25 11.25 -4.75 3.5 5.0 +3.0 16.0 4.0 26.0 97 126 1.82 152 181 2.5
pF V V V V V V V mA mA mA mA mA mA W mA mA W mV/K C
S D D D D D D D P P P P P P P P P P CT CT
-1.25 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU Range E, VCH = 7.0 V, VCL = -2.5 V -1.25 V < VDUTx < +6.0 V; PMU and PE disabled via SPI; PMU Range A, PMU Range B, PMU Range C, and PMU Range D, VCH = +7.0 V, VCL = -2.5 V -1.25 V < VDUTx < +6.0 V; PMU disabled and PE enabled via SPI; RCV active, VCH = +7.0 V, VCL = -2.5 V VTERM mode operation
VPLUS VDD VSS VCC VCOMP_VTT IPLUS ICC ICOMP_VTT IDD ISS IDD ISS
16.25 10.25 -5.25 3.1 3.3 -1.0 4.0 1.0 10.0 72 100 1.0 102 130 1.8
Defines PSRR conditions Defines PSRR conditions Defines PSRR conditions Defines PSRR conditions Defines PSRR conditions HVOUT disabled HVOUT enabled, RCV active, no load, VHH = 12 V Quiescent (SPI is static) Load power down (IOH = IOL = 0 mA) Load power down (IOH = IOL = 0 mA) Load power down (IOH = IOL = 0 mA) Load active off (IOH = IOL = 12 mA) Load active off (IOH = IOL = 12 mA) Load active off (IOH = IOL = 12 mA)
Temperature voltage available on Pin A1 at all times and on Pin K1 (MEASOUT01/TEMPSENSE) when selected (see Table 24 and Table 36) Referenced to VREF_GND; not referenced to VDUTGND Tested with 5 V applied
4.95
5 0.1
5.05 100
V A
D P
Rev. 0 | Page 4 of 52
ADATE304
DRIVER
VH - VL 200 mV (to meet dc and ac specifications). Table 2.
Parameter DC SPECIFICATIONS High Speed Differential Logic Input Characteristics (DATAxx, RCVxx) Input Termination Resistance Input Voltage Differential Common-Mode Voltage Input Bias Current Pin Output Characteristics Output High Range, VH Output Low Range, VL Output Term Range, VT Functional Amplitude (VH - VL) DC Output Current Limit Source DC Output Current Limit Sink Output Resistance, 50 mA ABSOLUTE ACCURACY Min Typ Max Unit Test Level Test Conditions/Comments
92 0.2 0.85 0.85 -20.0
100
108 1.0 2.35 3.5 +20.0
V V V A
P PF PF D P
Push 6 mA into xP pins 1 , force 1.3 V on xN pins1; measure voltage from xP to xN1, calculate resistance (V/I)
+2.2
Each pin tested at 2.85 V and 0.35 V while the other high speed pin remains open
-1.15 -1.25 -1.25 0.0 75 -120 45.0
+6.75 +6.65 +6.75 8.0 100 -100 47.0 120 -75 49.0
V V V V mA mA
D D D D P P P
VH, VL, VT Uncalibrated Accuracy VH, VL, VT Offset Tempco VH, VL, VT DNL VH, VL, VT INL VH, VL, VT Resolution DUTGND Voltage Accuracy VH, VL, VT Crosstalk
-250
-10
75 450 1 2.5 0.6
+250
+10 +1 +7
mV V/C mV mV mV mV mV
P CT CT P PF P CT
-7
1.3 2
Overall Voltage Accuracy VH, VL, VT DC PSRR AC SPECIFICATIONS Rise/Fall Times 0.2 V Programmed Swing 1.0 V Programmed Swing 2.0 V Programmed Swing 3.0 V Programmed Swing 3.0 V Programmed Swing 5.0 V Programmed Swing Rise-to-Fall Matching
10 15
mV mV/V
CT CT
Amplitude can be programmed to VH = VL, accuracy specifications apply when VH - VL 200 mV Driver high, VH = 6.75 V, short DUTx pin to -1.25 V, measure current Driver low, VL = -1.25 V, short DUTx pin to +6.75 V, measure current Source: driver high, VH = +3.0 V, IDUTx = +1 mA and +50 mA; sink: driver low, VL = 0.0 V, IDUTx = -1 mA and -50 mA; VDUT/IDUT VH tests done with VL = -2.5 V and VT= -2.5 V; VL tests done with VH = +7.5 V and VT = +7.5 V; VT tests done with VL = -2.5 V and VH = +7.5 V; unless otherwise specified Error measured at calibration points of 0 V and 5 V Measured at calibration points After two-point gain/offset calibration After two-point gain/offset calibration; measured over driver output ranges After two-point gain/offset calibration; range/number of DAC bits as measured at calibration points of 0 V and 5 V Over 0.1 V range; measured at endpoints of VH, VL, and VT functional range VL = -1.25 V: VH = -1.15 V +6.75 V, VT = -1.25 V +6.75 V; VH = +6.75 V: VL = -1.25 V +6.65 V, VT = -1.25 V +6.75 V; VT = +1.25 V: VL = -1.25 V +6.65 V, VH = -1.15 V +6.75 V; dc crosstalk on VL, VH, VT output level when other driver DACs are varied Sum of INL, crosstalk, DUTGND, and tempco over 5C, after gain/offset calibration Measured at calibration points Toggle DATAxx VH = 0.2 V, VL = 0.0 V, terminated; 20% to 80% VH = 1.0 V, VL = 0.0 V, terminated; 20% to 80% VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80% VH = 3.0 V, VL = 0.0 V, terminated; 20% to 80% VH = 3.0 V, VL = 0.0 V, unterminated; 10% to 90% VH = 5.0V, VL = 0.0 V, unterminated; 10% to 90% VH = 3.0 V, VL = 0.0 V, terminated; rise-to-fall within one channel
850
950 850 1150 1500 2000 3100 40
1350
ps ps ps ps ps ps ps
CB CB CB P/CB CB CB CB
Rev. 0 | Page 5 of 52
ADATE304
Parameter Minimum Pulse Width 1.0 V Programmed Swing Min Typ 1.7 1.7 2.0 2.2 2.7 2.7 Max Unit ns ns ns ns ns ns Test Level CB CB CB CB CB CB Test Conditions/Comments Toggle DATAxx VH = 1.0 V, VL = 0.0 V, terminated; timing error 75 ps VH = 1.0 V, VL = 0.0 V, terminated; less than 10% amplitude degradation VH = 2.0 V, VL = 0.0 V, terminated; timing error 75 ps VH = 2.0 V, VL = 0.0 V, terminated; less than 10% amplitude degradation VH = 3.0 V, VL = 0.0 V, terminated; timing error 75 ps VH = 3.0 V, VL = 0.0 V, terminated; less than 10% amplitude degradation VH = 2.0 V, VH = 0.0 V, terminated, 10% amplitude degradation Toggle DATAxx VH = 2.0 V, VL = 0.0 V, terminated VH = 2.0 V, VL = 0.0 V, terminated VH = 2.0 V, VL = 0.0 V, terminated Rising vs. falling Rising vs. rising, falling vs. falling VH = 3.0 V, VL = 0.0 V, terminated; 5% to 95% duty cycle; 1 MHz VH = 3.0 V, VL = 0.0 V, terminated Toggle DATAxx VH = 3.0 V, VL = 0.0 V, terminated VH = 3.0 V, VL = 0.0 V, terminated Toggle RCVxx VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; rising vs. falling VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated VH = 3.0 V, VT = 1.5 V, VL = 0.0 V, terminated; 20% to 80% Toggle RCVxx VH = +1.0 V, VL = -1.0 V, terminated 4.5 7.9 2.9 0.65 190 ns ns ns ns mV CB CB VH =+1.0 V, VL = -1.0 V, terminated; 20% to 80% CB CB CB
2.0 V Programmed Swing
3.0 V Programmed Swing
Maximum Toggle Rate 2.0 V Programmed Swing Dynamic Performance, Drive (VH to VL and VL to VH) Propagation Delay Time Propagation Delay Tempco Delay Matching Edge to Edge Channel to Channel Delay Change vs. Duty Cycle Overshoot and Undershoot Settling Time (VH to VL) To Within 3% of Final Value To Within 1% of Final Value Dynamic Performance, VT (VH or VL to VT and VT to VH or VL) Propagation Delay Time Delay Matching, Edge to Edge Propagation Delay Tempco Transition Time, Active to VT and VT to Active Dynamic Performance, Inhibit (VH or VL to/from Inhibit) Propagation Delay Time Active to Inhibit Inhibit to Active Transition Time Active to Inhibit Inhibit to Active I/O Spike
1
200
MHz
CB
3.0 3.0 80 30 30 30 4 25
ns ps/C ps ps ps mV ns ns
CB CT CB CB CB CB CB CB
3.7 150 4.0 1.0
ns ps ps/C ns
CB CB CT CB
VH = 0.0 V, VL = 0.0 V, terminated
The xP pins include DATA0P, DATA1P, RCV0P, and RCV1P; the xN pins include DATA0N, DATA1N, RCV0N, and RCV1N. For example, push 6 mA into the DATA0P pin, force 1.3 V into DATA0N, and measure the voltage from DATA0P to DATA0N.
Rev. 0 | Page 6 of 52
ADATE304
REFLECTION CLAMP
Clamp accuracy specifications apply when VCH > VCL. Table 3.
Parameter VCH Range Uncalibrated Accuracy Resolution Min -1.0 -200 Typ Max +6.75 +200 0.75 Unit V mV mV Test Level D P PF Test Conditions/Comments
50 0.6
DNL INL Tempco VCL Range Uncalibrated Accuracy Resolution -40
1 2 -0.3 -1.25 -200 +5.75 +200 0.75 +40
mV mV mV/C V mV mV
CT P CT D P PF
Driver high-Z, sinking 1 mA; VCH error measured at the calibration points of 0.0 V and 5.0 V Driver high-Z, sinking 1 mA; after two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points of 0.0 V and 5.0 V Driver high-Z, sinking 1 mA; after two-point gain/offset calibration Driver high-Z, sinking 1 mA; after two-point gain/offset calibration; measured over VCH range of -1.0 V to +6.75 V Measured at calibration points
50 0.6
DNL INL Tempco DC CLAMP CURRENT LIMIT VCH VCL DUTGND VOLTAGE ACCURACY -40
1 2 0.5 -120 60 -7 -85 85 1 -60 120 +7 +40
mV mV mV/C mA mA mV
CT P CT P P P
Driver high-Z, sourcing 1 mA; VCL error measured at the calibration points of 0.0 V and 5.0 V Driver high-Z, sourcing 1 mA; after two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points of 0.0 V and 5.0 V Driver high-Z, sourcing 1 mA; after two-point gain/offset calibration Driver high-Z, sourcing 1 mA; after two-point gain/offset calibration; measured over VCL range of -1.0 V to +5.75 V Measured at calibration points Driver high-Z, VCH = 0 V, VCL = -1.0 V, VDUTx = +5 V Driver high-Z, VCH = 6.75 V, VCL = 5.0 V, VDUTx = 0.0 V Over 0.1 V range; measured at the endpoints of VCH and VCL functional range
NORMAL WINDOW COMPARATOR
VOH tests done with VOL = -1.25 V; VOL tests done with VOH = 6.0 V, unless otherwise specified. Table 4.
Parameter DC SPECIFICATIONS Input Voltage Range Differential Voltage Range Comparator Input Offset Voltage Accuracy, Uncalibrated Comparator Threshold Resolution Min -1.25 0.1 -150 Typ Max +6.75 8.0 +150 1 Unit V V mV mV Test Level D D P PF Test Conditions/Comments
30 0.6
Comparator Threshold DNL Comparator Threshold INL
-7
1 1.3
+7
mV mV
CT P
Comparator Input Offset Voltage Tempco DUTGND Voltage Accuracy
100 -7 0.5 +7
V/C mV
CT P
Offset measured at the calibration points of 0.0 V and 5.0 V After two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points of 0 V and 5 V After two-point gain/offset calibration After two-point gain/offset calibration; measured over VOH, VOL range of -1.25 V to +6.75 V Measured at calibration points Over 0.1 V range; measured at endpoints of VOH and VOL functional range
Rev. 0 | Page 7 of 52
ADATE304
Parameter Comparator Uncertainty Range DC Hysteresis DC PSRR Digital Output Characteristics Internal Pull-Up Resistance to Comparator, COMP_VTT Pin Min Typ 6.0 0.5 5 40 50 60 Max Unit mV mV mV/V Test Level CB CB CT P Test Conditions/Comments VDUTx = 0 V, sweep comparator threshold to determine uncertainty region VDUTx = 0 V Measured at calibration points Pull 1 mA and 10 mA from Logic 1 leg and measure V to calculate resistance; measured V/9 mA; done for both comparator logic states Measured with 100 differential termination Measured with no external termination Measured with 100 differential termination Measured with no external termination Measured with each comparator leg terminated 50 to GND Input transition time = 800 ps, 10% to 90%; measured with each comparator leg terminated 50 to GND, unless otherwise specified VDUTx = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = +0.50 V, VOL = -1.25 V; low-side measurement: VOH = +6.75 V, VOL = +0.50 V VDUTx = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = +0.50 V, VOL = -1.25 V; low-side measurement: VOH = +6.75 V, VOL = +0.50 V VDUTx = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = +0.50 V, VOL = -1.25 V; low-side measurement: VOH = +6.75 V, VOL = +0.50 V
VCOMP_VTT Range Common-Mode Voltage Differential Voltage
3.3 VCOMP_VTT - 1.88 VCOMP_VTT - 2.075 400 250 500 450
5.0 VCOMP_VTT - 1.675 600
Rise/Fall Time, 20% to 80% AC SPECIFICATIONS
V V V mV mV ps
D CT P CT P CB
Propagation Delay, Input to Output
1.75
ns
CB
Propagation Delay Tempco
5
ps/C
CT
Propagation Delay Matching
High Transition to Low Transition High to Low Comparator Propagation Delay Change (with Respect To) Slew Rate, 800 ps, 1 ns, 1.2 ns, and 2.2 ns (10% to 90%)
200 50
ps ps
CB CB
50
ps
CB
Overdrive, 250 mV and 1.0 V
75
ps
CB
Pulse Width, Sweep 1.6 ns to 10 ns
75
ps
CB
Duty Cycle, 5% to 95%
50
ps
CB
Minimum Pulse Width
2.0
ns
CB
Input Equivalent Bandwidth, Terminated ERT High-Z Mode, 3 V, 20% to 80%
500 2.5
MHz ns
CB CB
VDUTx = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = +0.50 V, VOL = -1.25 V; low-side measurement: VOH = +6.75V, VOL = +0.50 V For 250 mV: VDUTx = 0 V to 0.5 V swing; for 1.0 V: VDUTx = 0 V to 1.25 V swing; Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = +0.25 V, VOL = -1.25 V; low-side measurement: VOH = +6.75 V, VOL = +0.25 V VDUTx = 0 V to 1.0 V swing @ 32.0 MHz, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = +0.5 V, VOL = -1.25 V; low-side measurement: VOH = +6.75 V, VOL = +0.5 V VDUTx = 0 V to 1.0 V swing @ 1.0 MHz, Driver VTERM mode, VT =0.0 V; high-side measurement: VOH = +0.50 V, VOL = -1.25 V; low-side measurement: VOH = +6.75 V, VOL = +0.50 V VDUTx = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; less than 12% amplitude degradation measured by shmoo VDUTx = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; as measured by shmoo VDUTx = 0 V to 3.0 V swing, driver high-Z; as measured by shmoo; input transition time of ~2000 ps, 10% to 90%
Rev. 0 | Page 8 of 52
ADATE304
DIFFERENTIAL COMPARATOR
VOH tests done with VOL = -1.1 V, VOL tests done with VOH = +1.1 V, unless otherwise specified. Table 5.
Parameter DC SPECIFICATIONS Input Voltage Range Operational Differential Voltage Range Maximum Differential Voltage Range Comparator Input Offset Voltage Accuracy, Uncalibrated VOH, VOL Resolution Min -1.25 0.05 Typ Max +4.5 1.1 8 +150 1 Unit V V V mV mV Test Level D D D P/CT PF Test Conditions/Comments
-150
35 0.6
VOH, VOL DNL VOH, VOL INL VOH, VOL Offset Voltage Tempco Comparator Uncertainty Range DC Hysteresis CMRR DC PSRR AC SPECIFICATIONS Propagation Delay, Input to Output -15
1 2.0 200 18 0.5 0.15 1.5 +15
mV mV V/C mV mV mV/V mV/V
CT P CT CB CB P CT
1
1.7
ns
CB
Propagation Delay Tempco
5
ps/C
CT
Propagation Delay Matching
Offset measured at differential calibration points +1.0 V and -1.0 V, with common mode = 0.0 V After two-point gain/offset calibration; range/number of DAC bits as measured at differential calibration points +1.0 V and -1.0 V, with common mode = 0.0 V After two-point gain/offset calibration; common mode = 0.0 V After two-point gain/offset calibration; measured over VOH, VOL range of -1.1 V to +1.1 V, common mode = 0.0 V Measured at calibration points VDUTx = 0 V, sweep comparator threshold to determine uncertainty region VDUTx = 0 V Offset measured at common-mode voltage points of -1.5 V and +4.5 V, with differential voltage = 0.0 V Measured at calibration points Input transition time = 800 ps, 10% to 90%, measured with each comparator leg terminated 50 to GND VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel
High Transition to Low Transition High-to-Low Comparator Propagation Delay Change (with Respect To)
100 50
ps ps
CB CB VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel VDUT0 = 0 V, for 250 mV: VDUT1 = 0 V to 0.5 V swing; for 750 mV: VDUT1 = 0 V to 1.0 V swing, Driver VTERM mode, VT = 0.0 V; VOH = -0.25 V; repeat for other DUT channel with comparator threshold = +0.25 V VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing @ 32 MHz, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing @ 1 MHz, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; repeat for other DUT channel
Slew Rate, 800 ps, 1 ns, 1.2 ns, and 2.2 ns (10% to 90%)
60
ps
CB
Overdrive, 250 mV and 750 mV
100
ps
CB
Pulse Width, Sweep from 1.6 ns to 10 ns
75
ps
CB
Duty Cycle, 5% to 95%
60
ps
CB
Rev. 0 | Page 9 of 52
ADATE304
Parameter Minimum Pulse Width Min Typ 2.5 Max Unit ns Test Level CB Test Conditions/Comments VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; less than 10% amplitude degradation measured by shmoo; repeat for other DUT channel VDUT0 = 0 V, VDUT1 = -0.5 V to +0.5 V swing, Driver VTERM mode, VT = 0.0 V; high-side measurement: VOH = 0.0 V, VOL = -1.1 V; low-side measurement: VOH = +1.1 V, VOL = 0.0 V; less than 22% amplitude degradation measured by shmoo; repeat for other DUT channel
Input Equivalent Bandwidth, Terminated
400
MHz
CB
ACTIVE LOAD
See the Truth Tables section and Table 29 for load control information. Table 6.
Parameter DC SPECIFICATIONS Input Characteristics VCOM Voltage Range VDUT Range VCOM Accuracy, Uncalibrated VCOM Resolution Min Typ Max Unit Test Level Test Conditions/Comments Load active on, RCV active, unless otherwise noted
-1.00 -1.25 -200
30 0.6
+6.50 +6.75 +200 1
V V mV mV
D D P PF
VCOM DNL VCOM INL DUTGND Voltage Accuracy Output Characteristics IOL Maximum Source Current Uncalibrated Offset Uncalibrated Gain Resolution
-7 -7
1 2 1
+7 +7
mV mV mV
CT P P
IOH = IOL = 6 mA, VCOM error measured at the calibration points of 0.0 V and 5.0 V IOH = IOL = 6 mA, after two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points of 0.0 V and 5.0 V IOH = IOL = 6 mA, after two-point gain/offset calibration IOH = IOL = 6 mA, after two-point gain/offset calibration; measured over VCOM range of -1.00 V to +6.50 V Over 0.1 V range; measured at end points of VCOM functional range
12 -600 -12
100 4 1.5
+600 +12 2
mA A % A
D P P PF
DNL INL 90% Commutation Voltage -80
3.0 20 +80 0.25
A A V
CT P P
IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL offset calculated from the calibration points of 1 mA and 11 mA IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, IOL gain calculated from the calibration points of 1 mA and 11 mA IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/ offset calibration; range/number of DAC bits as measured at the calibration points of 1 mA and 11 mA IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/offset calibration IOH = 0 mA, VCOM = 1.5 V, VDUTx = 0.0 V, after two-point gain/ offset calibration; measured over IOL range of 0 mA to 12 mA IOH = IOL = 12 mA, VCOM = 2.0 V, measure IOL reference at VDUTx = -1.0 V, measure IOL current at VDUTx = +1.75 V, ensure > 90% of reference current
IOH Maximum Sink Current Uncalibrated Offset Uncalibrated Gain Resolution
12 -600 -12
100 4 1.5
+600 +12 2
mA A % A
D P P PF
DNL
3.0
A
CT
IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH offset calculated from the calibration points of 1 mA and 11 mA IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, IOH gain calculated from the calibration points of 1 mA and 11 mA IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points of 1 mA and 11 mA IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/offset calibration
Rev. 0 | Page 10 of 52
ADATE304
Parameter INL 90% Commutation Voltage Min -80 Typ 20 Max +80 0.25 Unit A V Test Level P P Test Conditions/Comments IOL = 0 mA, VCOM = 1.5 V, VDUTx = 3.0 V, after two-point gain/ offset calibration; measured over IOH range of 0 mA to 12 mA IOH = IOL =12 mA, VCOM = 2.0 V, measure IOH reference at VDUTx = 5.0 V, measure IOH current at VDUTx = 2.25 V, ensure > 90% of reference current Measured at calibration points Load active on, unless otherwise noted Toggle RCV, DUTx terminated 50 to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = -1.25 V for IOH; measured from 50% point of RCVxP - RCVxN to 90% point of final output, repeat for drive low and high Toggle RCV, DUTx terminated 50 to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = -1.25 V for IOH; measured from 50% point of RCVxP - RCVxN to 90% point of final output, repeat for drive low and high Toggle RCV, DUTx terminated 50 to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = -1.25 V for IOH; active on vs. active off, repeat for drive low and high Toggle RCV, DUTx terminated 50 to GND, IOH = IOL = 0 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = -1.25 V for IOH; repeat for drive low and high Toggle RCV, DUTx terminated 50 to GND, IOH = IOL = 12 mA, VH = VL = 0 V, VCOM = +1.25 V for IOL and VCOM = -1.25 V for IOH; measured at 90% of final value
Output Current Tempco AC SPECIFICATIONS Dynamic Performance Propagation Delay, Load Active On to Load Active Off; 50%,90% Propagation Delay, Load Active Off to Load Active On; 50%, 90% Propagation Delay Matching
1.5
A/C
CT
7.3
ns
CB
10.3
ns
CB
3.0
ns
CB
Load Spike
190
mV
CB
Settling Time to 90%
1.9
ns
CB
PMU
FV is the force voltage, MV is the measure voltage, FI is the force current, MI is the measure current, FN is force nothing. Table 7.
Parameter FORCE VOLTAGE (FV) Current Range A Current Range B Current Range C Current Range D Current Range E Force Input Voltage Range at Output for All Ranges Force Voltage Uncalibrated Accuracy for Range C Force Voltage Uncalibrated Accuracy for All Ranges Force Voltage Offset Tempco for All Ranges Force Voltage Gain Tempco for All Ranges Forced Voltage INL Force Voltage Compliance vs. Current Load Min 32 2 200 20 2 -1.25 -100 25 25 25 10 -7 2 +7 Typ Max Unit mA mA A A A V mV mV V/C ppm/C mV Test Level D D D D D D P CT CT CT P PMU enabled, FV, Range C, PE disabled, error measured at calibration points of 0.0 V and 5.0 V PMU enabled, FV, PE disabled, error measured at calibration points of 0.0 V and 5.0 V; repeat for each PMU current range Measured at calibration points for each PMU current range Measured at calibration points for each PMU current range PMU enabled, FV, Range C, PE disabled, after two-point gain/offset calibration; measured over output range of -1.25 V to +6.75 V PMU enabled, FV, PE disabled, force -1.25 V, measure voltage while PMU sinking zero and full-scale current; measure V; force 6.75 V, measure voltage while PMU sourcing zero and full-scale current; measure V; repeat for each PMU current range Test Conditions/Comments
+6.75 +100
Range A Range B to Range E
4 1
mV mV
CT CT
Rev. 0 | Page 11 of 52
ADATE304
Parameter Current Limit, Source, and Sink Range A Min 108 Typ 140 Max 180 Unit %FS Test Level P Test Conditions/Comments PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to 6.0 V; source: force 2.5 V, short DUTx to -1.0 V; Range A FS = 32 mA, 108% FS = 35 mA, 180% FS = 58 mA PMU enabled, FV, PE disabled; sink: force 2.5 V, short DUTx to 6.0 V; source: force 2.5 V, short DUTx to -1.0 V; repeat for each PMU current range; example: Range B FS = 2 mA, 120 % FS = 2.4 mA, 180% FS = 3.6 mA Over 0.1 V range; measured at endpoints of FV functional range VDUTx externally forced to 0.0V, unless otherwise specified; ideal MEASOUT transfer functions: VMEASOUT01 [V] = (IMEASOUT01 x 5/FSR) + 2.5 + VDUTGND I(VMEASOUT01) [A] = (VMEASOUT01 - VDUTGND - 2.5) x FSR/5
Range B to Range E
120
145
180
%FS
P
DUTGND Voltage Accuracy MEASURE CURRENT (MI)
-7
1
+7
mV
P
Measure Current, Pin DUTx Voltage Range for All Ranges Measure Current Uncalibrated Accuracy Range A Range B Range C Range D Range E Measure Current Offset Tempco Range A Range B Range C Range D and Range E Measure Current Gain Error, Nominal Gain = 1 Range A Range B Range C to Range E Measure Current Gain Tempco Range A Range B to Range E Measure Current INL Range A
-1.5
+6.0
V
D
500 -400 3.0 2.00 0.30 0.08 +400
A A A A A
CT P CT CT CT
PMU enabled, FIMI, Range A, PE disabled, error at calibration points -25 mA and +25 mA, error = (I(VMEASOUT01) - IDUTx) PMU enabled, FIMI, Range B, PE disabled, error at calibration points -1.6 mA and +1.6 mA, error = (I(VMEASOUT01) - IDUTx) PMU enabled, FIMI, PE disabled, error at calibration points of 80% FS, error = (I(VMEASOUT01)1 - IDUTx) PMU enabled, FIMI, PE disabled, error at calibration points of 80% FS, error = (I(VMEASOUT01) - IDUTx) PMU enabled, FIMI, PE disabled, error at calibration points of 80% FS, error = (I(VMEASOUT01) - IDUTx) Measured at calibration points Measured at calibration points Measured at calibration points Measured at calibration points
2 25 5 1
A/C nA/C nA/C nA/C
CT CT CT CT
2.5 -20 2 4 +20
% % %
CT P CT
PMU enabled, FIMI, PE disabled, gain error from calibration points 80% FS PMU enabled, FIMI, Range B, PE disabled, gain error from calibration points 1.6 mA PMU enabled, FIMI, PE disabled, gain error from calibration points 80% FS Measured at calibration points
300 50 0.05
ppm/C ppm/C %FSR
CT CT CT PMU enabled, FIMI, Range A, PE disabled, after two-point gain/offset calibration, measured over FSR output of -32 mA to +32 mA PMU enabled, FIM,I Range B, PE disabled, after two-point gain/ offset calibration measured over FSR output of -2 mA to +2 mA PMU enabled, FIMI, PE disabled, after two-point gain/offset calibration; measured over FSR output PMU enabled, FVMI, Range B, PE disabled, force -1 V and +5 V into load of 1 mA; measure I reported at MEASOUT01 Over 0.1 V range; measured at endpoints of MI functional range
Range B Range B to Range E FVMI DUT Pin Voltage Rejection DUTGND Voltage Accuracy
-0.02 0.01 -0.01 2.5
+0.02
%FSR %FSR
P CT P CT
+0.01
%FSR/V mV
Rev. 0 | Page 12 of 52
ADATE304
Parameter FORCE CURRENT (FI) Force Current, DUTx Pin Voltage Range for All Ranges Force Current Uncalibrated Accuracy Range A Range B Range C Range D Range E Force Current Offset Tempco Range A Range B Range C to Range E Forced Current Gain Error, Nominal Gain = 1 Forced Current Gain Tempco Range A Range B to Range E Force Current INL Range A Min Typ Max Unit Test Level Test Conditions/Comments VDUTx externally forced to 0.0V, unless otherwise specified, ideal force current transfer function: IFORCE = (PMUDAC - 2.5) x (FSR/5)
-1.25
+6.75
V
D
-5.0 -400 -40 -4 -400
0.5 40 4 0.4 75
+5.0 +400 +40 +4 +400
mA A A A nA
P P P P P
PMU enabled, FIMI, Range A, PE disabled, error at calibration points of -25 mA and +25 mA PMU enabled, FIMI, Range B, PE disabled, error at calibration points of -1.6 mA and 1.6 mA PMU enabled, FIMI, Range C, PE disabled, error at calibration points of 80% FS PMU enabled, FIMI, Range D, PE disabled, error at calibration points of 80% FS PMU enabled, FIMI, Range E, PE disabled, error at calibration points of 80% FS Measured at calibration points Measured at calibration points Measured at calibration points PMU enabled, FIMI, PE disabled, gain error from calibration points of 80% FS Measured at calibration points
-20
1 80 4 4
+20
A/C nA/C nA/C %
CT CT CT P
-500 75 -0.3 0.05 +0.3
ppm/C ppm/C %FSR
CT CT P PMU enabled, FIMI, Range A, PE disabled, after two-point gain/offset calibration; measured over FSR output of -32 mA to +32 mA PMU enabled, FIMI, PE disabled, after two-point gain/offset calibration; measured over FSR output PMU enabled, FIMV, PE disabled; force positive full-scale current driving -1.5 V and +6.0 V, measure I @ DUTx pin; force negative full-scale current driving -1.25 V and +6.75 V, measure I @ DUTx pin
Range B to Range E Force Current Compliance vs. Voltage Load
-0.2
0.015
+0.2
%FSR
P
Range A to Range D Range E MEASURE VOLTAGE Measure Voltage Range Measure Voltage Uncalibrated Accuracy Measure Voltage Offset Tempco Measure Voltage Gain Error Measure Voltage Gain Tempco Measure Voltage INL
-0.6 -1.0 -1.5 -25
0.06 0.1
+0.6 +1.0 +6.0 +25
%FSR %FSR V mV V/C % ppm/C mV
P P D P CT P CT P
2.0 10 0.01 25 1
-0.2
+0.2
-7
+7
Rejection of Measure V vs. IDUTx
-1.5
0.1
+1.5
mV
P
PMU enabled, FVMV, Range B, PE disabled, error at calibration points of 0 V and 5 V, error = (VMEASOUT01 - VDUTx) Measured at calibration points PMU enabled, FVMV, Range B, PE disabled, gain error from calibration points of 0 V and 5 V Measured at calibration points PMU enabled, FVMV, Range B, PE disabled, after two-point gain/offset calibration; measured over output range of -1.25 V to +6.75 V PMU enabled, FVMV, Range D, PE disabled, force 0 V into load of -10 A and +10 A; measure V reported at MEASOUT01
Rev. 0 | Page 13 of 52
ADATE304
Parameter MEASOUT01 DC CHARACTERISTICS MEASOUT01 Voltage Range DC Output Current MEASOUT01 Pin Output Impedance Min -1.5 25 Typ Max +6.0 4 200 Unit V mA Test Level D D P Test Conditions/Comments
Output Leakage Current when Tristated Output Short-Circuit Current
-1 -25
+1 +25
A mA
P P
PMU enabled, FVMV, PE disabled; source resistance: PMU force +6.75 V and load with 0 mA and +4 mA; sink resistance: PMU force -1.25 V and load with 0 mA and -4 mA; resistance = V/I at MEASOUT01 pin Tested at -1.25 V and +6.75 V PMU enabled, FVMV, PE disabled; source: PMU force +6.75 V, short MEASOUT01 to -1.25 V; sink: PMU force -1.25 V, short MEASOUT01 to +6.75 V
VOLTAGE CLAMPS Low Clamp Range (VCL) High Clamp Range (VCH) Positive Clamp Voltage Droop
-1.25 0.75 -300
+10
+4.75 6.75 +300
V V mV
D D P
Negative Clamp Voltage Droop
-300
-10
+300
mV
P
Uncalibrated Accuracy
-250
100
+250
mV
P
INL
-70
5
+70
mV
P
DUTGND Voltage Accuracy SETTLING/SWITCHING TIMES Voltage Force Settling Time to 0.1% of Final Value Range A, 200 pF and 2000 pF Load Range B, 200 pF and 2000 pF Load Range C, 200 pF and 2000 pF Load Range D, 200 pF and 2000 pF Load Range E, 200 pF and 2000 pF Load Voltage Force Settling Time to 1.0% of Final Value Range A, 200 pF and 2000 pF Load Range B, 200 pF and 2000 pF Load Range C, 200 pF and 2000 pF Load Range D, 200 pF Load Range D, 2000 pF Load Range E, 200 pF Load Range E, 2000 pF Load
1
mV
CT
PMU enabled, FIMI, Range A, PE disabled, PMU clamps enabled, VCH = +5.0 V, VCL = -1.0 V, PMU force 2.0 mA and 32 mA into open; V seen at DUTx pin PMU enabled, FIMI, Range A, PE disabled, PMU clamps enabled, VCH = +5.0 V, VCL = -1.0 V, PMU force -2.0 mA and -32 mA into open; V seen at DUTx pin PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled, PMU force 1 mA into open; VCH errors at calibration points 1.0 V and 5.0 V; VCL errors at the calibration points 0.0 V and 4.0 V PMU enabled, FIMI, Range B, PE disabled, PMU clamps enabled, PMU force 1 mA into open; after two-point gain/offset calibration; measured over PMU clamp range Over 0.1 V range; measured at endpoints of PMU clamp functional range SCAP = 330 pF, FFCAP = 220 pF PMU enabled, FV, PE disabled, program PMUDAC steps of 500 mV and 5.0 V; simulation of worst case, 2000 pF load, PMUDAC step of 5.0 V
15 20 124 1015 3455
s s s s s
S S S S S PMU enabled, FV, PE disabled, start with PMUDAC programmed to 0.0 V, program PMUDAC to 500 mV
14 14 14 45 45 45 225
s s s s s s s
CB CB CB CB CB CB CB
Rev. 0 | Page 14 of 52
ADATE304
Parameter Voltage Force Settling Time to 1.0% of Final Value Range A, 200 pF and 2000 pF Load Range B, 200 pF Load Range B, 2000 pF Load Range C, 200 pF Load Range C, 2000 pF Load Range D, 200 pF Load Range D, 2000 pF Load Range E, 200 pF Load Range E, 2000 pF Load Current Force Settling Time to 0.1% of Final Value Range A, 200 pF in Parallel with 120 Range B, 200 pF in Parallel with 1.5 k Range C, 200 pF in Parallel with 15.0 k Range D, 200 pF in Parallel with 150 k Range E, 200 pF in Parallel with 1.5 M Current Force Settling Time to 1.0% of Final Value Range A, 200 pF in Parallel with 120 Range B, 200 pF in Parallel with 1.5 k Range C, 200 pF in Parallel with 15.0 k Range D, 200 pF in Parallel with 150 k Range E, 200 pF in Parallel with 1.5 M INTERACTION AND CROSSTALK Measure Voltage Channel-toChannel Crosstalk Min Typ Max Unit Test Level Test Conditions/Comments PMU enabled, FV, PE disabled, start with PMUDAC programmed to 0.0 V, program PMUDAC to 5.0 V
4.0 4.2 4.2 5.8 19 50 210 360 610
s s s s s s s s s
CB CB CB CB CB CB CB CB CB PMU enabled, FI, PE disabled, start with PMUDAC programmed to 0 current, program PMUDAC to FS current
8.2 9.4 30 281 2668
s s s s s
S S S S S PMU enabled, FI, PE disabled, start with PMUDAC programmed to 0 current, program PMUDAC to FS current
4.2 4.3 8.1 205 505
s s s s s
CB CB CB CB CB
0.125
%FSR
CT
Measure Current Channel-toChannel Crosstalk
0.01
%FSR
CT
PMU enabled, FIMV, PE disabled, Range B, forcing 0 mA into 0 V load; other channel: Range A, forcing a step of 0 mA to 25 mA into 0 V load; report V of MEASOUT01 pin under test; 0.125% x 8.0 V = 10 mV PMU enabled, FVMI, PE disabled, Range E, forcing 0 V into 0 mA current load; other channel: Range E, forcing a step of 0 V to 5 V into 0 mA current load; report V of MEASOUT01 pin under test; 0.01% x 5.0 V = 0.5 mV
Rev. 0 | Page 15 of 52
ADATE304
EXTERNAL SENSE (PMUS_CHx)
Table 8.
Parameter EXTERNAL SENSE (PMUS_CHX) Voltage Range Input Leakage Current Min -1.25 -20 Typ Max +6.75 +20 Unit V nA Test Level D P Test Conditions/Comments
Tested at -1.25 V and +6.75 V
DUTGND INPUT
Table 9.
Parameter DUTGND INPUT Input Voltage Range, Referenced to GND Input Bias Current Min -0.1 1 Typ Max +0.1 100 Unit V A Test Level D P Test Conditions/Comments
Tested at -100 mV and +100 mV
SERIAL PERIPHERAL INTERFACE
Table 10.
Parameter SERIAL PERIPHERAL INTERFACE Serial Input Logic High Serial Input Logic Low Input Bias Current SCLK Clock Rate SCLK Pulse Width SCLK Crosstalk on DUTx Pin Serial Output Logic High Serial Output Logic Low Update Time Min 1.8 0 -10 Typ Max VCC 0.7 +10 Unit V V A MHz ns mV V V s Test Level PF PF P PF CT CB PF PF D Test Conditions/Comments
1 50 9 8
Tested at 0.0 V and 3.3 V
VCC - 0.4 0 10
VCC 0.8
PE disabled, PMU FV enabled and forcing 0 V Sourcing 2 mA Sinking 2 mA Maximum delay time required for the part to enter a stable state after a serial bus
Rev. 0 | Page 16 of 52
ADATE304
HVOUT DRIVER
Table 11.
Parameter VHH BUFFER Voltage Range Output High Output Low Accuracy Uncalibrated Offset Tempco Resolution -500 100 1 1.21 Min 5.9 13.5 Typ Max VPLUS - 3.25 Unit V V V mV mV/C mV Test Level D P P P CT PF Test Conditions/Comments VHH = (VT + 1 V) x 2 + DUTGND VPLUS = 16.75 V nominal; in this condition, VHVOUT max = 13.5 V VHH mode enabled, RCV active, VHH level = full scale, sourcing 15 mA VHH mode enabled, RCV active, VHH level = zero scale, sinking 15 mA VHH mode enabled, RCV active, VHVOUT error measured at the calibration points of 7 V and 12 V Measured at calibration points VHH mode enabled, RCV active, after two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points of 7 V and 12 V VHH mode enabled, RCV active, after two-point gain/offset calibration; measured over VHH range of 5.9 V to 13.5 V Over 0.1 V range; measured at endpoints of VHH functional range VHH mode enabled, RCV active, source: VHH = 10.0 V, IHVOUT = 0 mA and 15 mA; sink: VHH = 6.5 V, IHVOUT = 0 mA and -15 mA; V/I VHH mode enabled, RCV active, VHH = 10.0 V, short HVOUT pin to 5.9 V, measure current VHH mode enabled, RCV active, VHH = 6.5 V, short HVOUT pin to 14.1 V, measure current VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH = 3.0 V; 20% to 80%, for DATA = high and DATA = low VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH = 3.0 V; 20% to 80%, for DATA = high and DATA = low VHH mode enabled, toggle RCV, VHH = 13.5 V, VL = VH = 3.0 V; for DATA = high and DATA = low
5.9 +500
1.5
INL DUTGND Voltage Accuracy Output Resistance
-30
15 1 1
+30
mV mV
P CT P
10
mA mA ns ns mV
DC Output Current Limit Source DC Output Current Limit Sink Rise Time (From VL or VH to VHH) Fall Time (From VHH to VL or VH) Preshoot, Overshoot, and Undershoot VL/VH BUFFER Voltage Range Accuracy Uncalibrated Offset Tempco Resolution
60 -100 200 26 125
100 -60
P P CB CB CB
-0.1 -500
100 1 0.61
+6.0 +500
V mV mV/C mV
D P CT PF
0.75
INL
-20
4
+20
mV
P
DUTGND Voltage Accuracy Output Resistance 45
2 48 50
mV
CT P
DC Output Current Limit Source DC Output Current Limit Sink Rise Time (VL to VH) Fall Time (VH to VL) Preshoot, Overshoot, and Undershoot
60 -100 11 11.3 54
100 -60
mA mA ns ns mV
P P CB CB CB
VHH mode enabled, RCV inactive, error measured at the calibration points 0 V and 5 V Measured at calibration points VHH mode enabled, RCV inactive, after two-point gain/offset calibration; range/number of DAC bits as measured at the calibration points 0 V and 5 V VHH mode enabled, RCV inactive, after two-point gain/offset calibration; measured over range of -0.1 V to +6.0 V Over 0.1 V range; measured at endpoints of VH and VL, functional range VHH mode enabled, RCV inactive, source: VH = 3.0 V, IHVOUT = +1 mA and +50 mA; sink: VL = 2.0 V, IHVOUT = -1 mA and -50 mA; V/I VHH mode enabled, RCV inactive, VH = +6.0 V, short HVOUT pin to -0.1 V, DATA high, measure current VHH mode enabled, RCV inactive, VL = -0.1 V, short HVOUT pin to +6.0 V, DATA low, measure current VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V, toggle DATA; 20% to 80% VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V, toggle DATA; 20% to 80% VHH mode enabled, RCV inactive, VL = 0.0 V, VH = 3.0 V, toggle DATA
Rev. 0 | Page 17 of 52
ADATE304
OVERVOLTAGE DETECTOR (OVD)
Table 12.
Parameter DC CHARACTERISTICS Programmable Voltage Range Accuracy Uncalibrated Hysteresis LOGIC OUTPUT CHARACTERISTICS Off State Leakage Maximum On Voltage @ 100 A Propagation Delay Min -2.25 -200 112 10 0.2 1.9 1000 0.7 Typ Max +7.0 +200 Unit V mV mV nA V s Test Level D P CB P P CB Disable OVD alarm, apply 3.3 V to OVD pin, measure leakage current Activate alarm, force 100 A into OVD pin, measure active alarm voltage For OVD high: DUTx = 0 V to +6 V swing, OVD high = +3.0 V, OVD low = -2.25 V; for OVD low: DUTx = 0 V to +6 V swing, OVD high = +7.0 V, OVD low = +3.0 V Test Conditions/Comments
OVD offset errors measured at programmed levels of +7.0 V and -2.25 V
16-BIT DAC MONITOR MUX
Table 13.
Parameter DC CHARACTERISTICS Programmable Voltage Range Output Resistance Min -2.5 16 Typ Max +7.5 Unit V k Test Level D CT Test Conditions/Comments
PMUDAC = 0.0 V, FV, I = 0, 200 A; V/I
Rev. 0 | Page 18 of 52
ADATE304 ABSOLUTE MAXIMUM RATINGS
Table 14.
Parameter Supply Voltages Positive Supply Voltage (VDD to GND) Positive VCC Supply Voltage (VCC to GND) Negative Supply Voltage (VSS to GND) Supply Voltage Difference (VDD to VSS) Reference Ground (DUTGND to GND) AGND to DGND VPLUS Supply Voltage (VPLUS to GND) Input Voltages Input Common-Mode Voltage Short-Circuit Voltage1 High Speed Input Voltage2 High Speed Differential Input Voltage3 VREF DUTx I/O Pin Current DCL Maximum Short-Circuit Current4 Temperature Operating Temperature, Junction Storage Temperature Range
1
THERMAL RESISTANCE
Rating -0.5 V to +11.5 V -0.5 V to +4.0 V -6.25 V to +0.5 V -1.0 V to +16.5 V -0.5 V to +0.5 V -0.5 V to +0.5 V -0.5 V to +17.5 V VSS to VDD -3.0 V to +8.0 V 0.0 V to VCC 0.0 V to VCC -0.5 V to +5.5 V 140 mA 125C -65C to +150C
Table 15. Thermal Resistance
Package Type 84-Ball CSP_BGA JA 31.1 JC 0.51
EXPLANATION OF TEST LEVELS
D S P PF CT CB Definition Design verification simulation 100% production tested Functionally checked during production test Characterized on tester Characterized on bench
ESD CAUTION
RL = 0 , VDUT continuous short-circuit condition (VH, VL, VT, high-Z, VCOM, clamp modes). 2 DATAxP, DATAxN, RCVxP, RCVxN, under source RL = 0 . 3 DATAxP to DATAxN, RCVxP, RCVxN. 4 RL = 0 , VDUTx = -3 V to +8 V; DCL current limit. Continuous short-circuit condition. ADATE304 must current limit and survive continuous short circuit.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Rev. 0 | Page 19 of 52
ADATE304 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
10 9 8 7 6 5 4 3 2 1 A HVOUT PMUS_CH0 VSSO_0 (DRIVE) DUT0 VDDO_0 (DRIVE) VDDO_1 (DRIVE) DUT1 VSSO_1 (DRIVE) PMUS_CH1 TEMPSENSE
B
VPLUS
SCAP0
VSS
AGND
VDD
VDD
AGND
VSS
SCAP1
VDD/VDD_ TMPSNS
C
FFCAP_0B
AGND
DATA0N
VSS
VDD
VDD
VSS
DATA1N
AGND
FFCAP_1B
D
OVD_CH0
VDD
DATA0P
DATA1P
VDD
OVD_CH1
E
FFCAP_0A
VSS
RCV0N
RCV1N
VSS
FFCAP_1A
F
AGND
AGND
RCV0P
RCV1P
AGND
AGND
G
COMP_QL0P COMP_QL0N COMP_VTT0
COMP_VTT1 COMP_QL1N COMP_QL1P
H
COMP_QH0P COMP_QH0N
AGND
VSS
VDD
VDD
VSS
AGND
COMP_QH1N COMP_QH1P
J
AGND
AGND
AGND
RST
SDIN
DGND
DAC16_MON
AGND
AGND
AGND
Figure 2. Pin Configuration
Rev. 0 | Page 20 of 52
07279-002
K
VREF_GND
VREF
AGND
VCC
SCLK
SDOUT
CS
AGND
DUTGND
MEASOUT01/ TEMPSENSE
ADATE304
Table 16. Pin Function Descriptions
Pin No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 D1 D2 D3 D8 D9 D10 E1 E2 E3 E8 E9 E10 F1 F2 F3 F8 F9 F10 G1 G2 G3 G8 Mnemonic TEMPSENSE PMUS_CH1 VSSO_1 (Drive) DUT1 VDDO_1 (Drive) VDDO_0 (Drive) DUT0 VSSO_0 (Drive) PMUS_CH0 HVOUT VDD/VDD_TMPSNS SCAP1 VSS AGND VDD VDD AGND VSS SCAP0 VPLUS FFCAP_1B AGND DATA1N VSS VDD VDD VSS DATA0N AGND FFCAP_0B OVD_CH1 VDD DATA1P DATA0P VDD OVD_CH0 FFCAP_1A VSS RCV1N RCV0N VSS FFCAP_0A AGND AGND RCV1P RCV0P AGND AGND COMP_QL1P COMP_QL1N COMP_VTT1 COMP_VTT0 Description Temperature Sense Output PMU External Sense Path Channel 1 Driver Output Supply (-5.0 V) Channel 1 Device Under Test Channel 1 Driver Output Supply (+10.75 V) Channel 1 Driver Output Supply (+10.75 V) Channel 0 Device Under Test Channel 0 Driver Output Supply (-5.0 V) Channel 0 PMU External Sense Path Channel 0 High Voltage Driver Output Temperature Sense Supply (+10.75 V) PMU Stability Capacitor Connection Channel 1 (330 pF) Supply (-5.0 V) Analog Ground Supply (+10.75 V) Supply (+10.75 V) Analog Ground Supply (-5.0 V) PMU Stability Capacitor Connection Channel 0 (330 pF) Supply (+16.75 V) PMU Feedforward Capacitor Connection B Channel 1 (220 pF) Analog Ground Driver Data Input (Negative) Channel 1 Supply (-5.0 V) Supply (+10.75 V) Supply (+10.75 V) Supply (-5.0 V) Driver Data Input (Negative) Channel 0 Analog Ground PMU Feedforward Capacitor Connection B Channel 0 (220 pF) Overvoltage Detection Flag Output Channel 1 Supply (+10.75 V) Driver Data Input (Positive) Channel 1 Driver Data Input (Positive) Channel 0 Supply (+10.75 V) Overvoltage Detection Flag Output Channel 0 PMU Feedforward Capacitor Connection A Channel 1 (220 pF) Supply (-5.0 V) Receive Data Input (Negative) Channel 1 Receive Data Input (Negative) Channel 0 Supply (-5.0 V) PMU Feedforward Capacitor Connection A Channel 0 (220 pF) Analog Ground Analog Ground Receive Data Input (Positive) Channel 1 Receive Data Input (Positive) Channel 0 Analog Ground Analog Ground Low-Side Comparator Output (Positive) Channel 1 Low-Side Comparator Output (Negative) Channel 1 Comparator Supply Termination Channel 1 Comparator Supply Termination Channel 0
Rev. 0 | Page 21 of 52
ADATE304
Pin No. G9 G10 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 J1 J2 J3 J4 J5 J6 J7 J8 J9 J10 K1 K2 K3 K4 K5 K6 K7 K8 K9 K10 Mnemonic COMP_QL0N COMP_QL0P COMP_QH1P COMP_QH1N AGND VSS VDD VDD VSS AGND COMP_QH0N COMP_QH0P AGND AGND AGND DAC16_MON DGND SDIN RST AGND AGND AGND MEASOUT01/TEMPSENSE DUTGND AGND CS SDOUT SCLK VCC AGND VREF VREF_GND Description Low-Side Comparator Output (Negative) Channel 0 Low-Side Comparator Output (Positive) Channel 0 High-Side Comparator Output (Positive) Channel 1 High-Side Comparator Output (Negative) Channel 1 Analog Ground Supply (-5.0 V) Supply (+10.75 V) Supply (+10.75 V) Supply (-5.0 V) Analog Ground High-Side Comparator Output (Negative) Channel 0 High-Side Comparator Output (Positive) Channel 0 Analog Ground Analog Ground Analog Ground 16-Bit DAC Monitor Mux Output Digital Ground Serial Peripheral Interface (SPI) Data In Serial Peripheral Interface (SPI) Reset Analog Ground Analog Ground Analog Ground Muxed Output Shared by PMU MEASOUT Channel 0, PMU MEASOUT Channel 1/ Temperature Sense and Temperature Sense GND Reference DUT Ground Reference Analog Ground Serial Peripheral Interface (SPI) Chip Select Serial Peripheral Interface (SPI) Data Out Serial Peripheral Interface (SPI) Clock Supply (+3.3 V) Analog Ground +5 V DAC Reference Voltage DAC Ground Reference
Rev. 0 | Page 22 of 52
ADATE304 TYPICAL PERFORMANCE CHARACTERISTICS
0.30 0.25 0.20
VOLTAGE (V)
VOLTAGE (V) 1.8
0.5V
1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 1V 2V 3V
0.15 0.10 0.05 0 -0.05 0.2V
0
07279-003
0
2
4
6
8
10 TIME (ns)
12
14
16
18
20
0
0.5
1.0
1.5
2.0
2.5 3.0 TIME (ns)
3.5
4.0
4.5
5.0
Figure 3. Driver Small Signal Response; VH = 0.2 V, 0.5 V; VL = 0.0 V; 50 Termination
1.8 1.6 1.4 1.2 3V
Figure 6. 50 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V, 50 Termination
1.8 1.6 1.4 1.2
VOLTAGE (V)
3V
VOLTAGE (V)
1.0 0.8 0.6 0.4 0.2 0
2V
1.0 0.8 0.6 0.4 0.2 0
2V
1V
1V
07279-004
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (ns)
Figure 4. Driver Large Signal Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V; 50 Termination
6 5V 5 4
VOLTAGE (V)
Figure 7. 100 MHz Driver Response; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V; 50 Termination
1.6 1.4 1.2
VOLTAGE (V)
3V
3 2 1 0 -1
3V
1.0 0.8 0.6 0.4 0.2
2V
1V
1V
07279-005
0
2
4
6
8
10 12 TIME (ns)
14
16
18
20
0
1
2
3
4
5 6 TIME (ns)
7
8
9
10
Figure 5. Driver Large Signal Response; VH = 1.0 V, 3.0 V, 5.0 V; VL = 0.0 V; 500 Termination
Figure 8. Response at 200 MH; VH = 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V; 50 Termination
Rev. 0 | Page 23 of 52
07279-008
0
07279-007
-0.2
-0.2
07279-006
-0.2
ADATE304
1.6 3V 1.4 1.2 0.5 0.4 2V 0.6
VOLTAGE (V)
VOLTAGE (V)
1.0 0.8 0.6
0.3 0.2 0.1 0
1V 0.4 0.5V 0.2
07279-009
0
1
2
3
4
5 TIME (ns)
6
7
8
9
10
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (ns)
Figure 9. 300 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, 3.0 V; VL = 0.0 V; 50 Termination
1.0 0.9 0.8 0.7 2V
Figure 12. Driver Active (VH and VL) to and from VTERM Transition; VH = 1.0 V, VT = 0.5 V, VL = 0.0 V
1.2 1.0 0.8
VOLTAGE (V)
VOLTAGE (V)
0.6 0.5 0.4 0.3 0.5V 0.2 0.1
07279-010
0.6 0.4 0.2 0
1V
0
0.5
1.0
1.5
2.0 2.5 3.0 TIME (ns)
3.5
4.0
4.5
5.0
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 TIME (ns)
Figure 10. 400 MHz Driver Response; VH = 0.5 V, 1.0 V, 2.0 V, VL = 0.0 V; 50 Termination
1.2
Figure 13. Driver Active (VH and VL) to and from VTERM Transition; VH = 2.0 V, VT = 1.0 V, VL = 0.0 V
1.6 1.4 1.2
1.0
0.8 VOLTAGE (V)
VOLTAGE (V)
1.0 0.8 0.6 0.4 0.2 0
07279-011
0.6
0.4
0.2
200
250 300 FREQUENCY (MHz)
350
0
2
4
6
8
10 TIME (ns)
12
14
16
18
20
Figure 11. Driver Toggle Rate, VH = 2.0 V, VL = 0.0 V, 50 Termination
Figure 14. Driver Active (VH and VL) to and from VTERM Transition; VH = 3.0 V, VT = 1.5 V, VL = 0.0 V
Rev. 0 | Page 24 of 52
07279-014
0
-0.2
07279-013
0
-0.2
07279-012
0
-0.1
ADATE304
20 0.2V NEG
TRAILING EDGE ERROR (ps)
20 2V POS 0
TRAILING EDGE ERROR (ps)
0
-20
2V NEG
-20
0.2V POS
-40
-40
-60
-60
-80
07279-015
1
2
3 4 PULSEWIDTH (ns)
5
6
7
8 9 10
1
2
3 4 PULSEWIDTH (ns)
5
6
7
8 9 10
Figure 15. Driver Minimum Pulse Width; VH = 0.2 V, VL = 0.0 V
20
Figure 18. Driver Minimum Pulse Width; VH = 2.0 V, VL = 0.0 V
20
TRAILING EDGE ERROR (ps)
TRAILING EDGE ERROR (ps)
0
0.5V NEG
0
3V POS
-20 3V NEG -40
-20
0.5V POS
-40
-60
-60
-80
07279-016
1
2
3 4 PULSEWIDTH (ns)
5
6
7
8 9 10
1
2
3 4 PULSE WIDTH (ns)
5
6
7
8 9 10
Figure 16. Driver Minimum Pulse Width; VH = 0.5 V, VL = 0.0 V
20 1V NEG 0 TRAILING EDGE ERROR (ps) 1V POS
Figure 19. Driver Minimum Pulse Width; VH = 3.0 V, VL = 0.0 V
1.0
0.5
LINEARITY ERROR (mV)
-20
0
-40
-0.5
-60
-1.0
-80
-1.5
07279-017
1
2
3 4 PULSEWIDTH (ns)
5
6
7
8 9 10
-1
0
1 2 3 4 5 DRIVER OUTPUT VOLTAGE (V)
6
7
Figure 17. Driver Minimum Pulse Width; VH = 1.0 V, VL = 0.0 V
Figure 20. Driver VH Linearity Error
Rev. 0 | Page 25 of 52
07279-020
-100
-2.0 -2
07279-019
-80
-100
07279-018
-80
-100
ADATE304
1.0
120 100
DRIVER OUTPUT CURRENT (mA)
07279-021
0.5
LINEARITY ERROR (mV)
80 60 40 20 0 -20 -2
0
-0.5
-1.0
-1
0 1 2 3 4 DRIVER OUTPUT VOLTAGE (V)
5
6
-1
0
1
2 3 VDUTx (V)
4
5
6
7
Figure 21. Driver VL Linearity Error
0.8 0.6 0.4
Figure 24. Driver Output Current Limit; Driver Programmed to -1.25 V; VDUTx Swept from -1.25 V to +6.75 V
20 0 DRIVER OUTPUT CURRENT (mA) -20 -40 -60 -80 -100 -120 -2
LINEARITY ERROR (mV)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
07279-022
-1
0
1 2 3 4 5 DRIVER OUTPUT VOLTAGE (V)
6
7
-1
0
1
2 3 VDUTx (V)
4
5
6
7
Figure 22. Driver VT Linearity Error
48.0 47.8
DRIVER OUTPUT RESISTANCE ()
Figure 25. Driver Output Current Limit; Driver Programmed to 6.75 V; VDUTx Swept from -1.25 V to +6.75 V
8 7 6
47.6 47.4 47.2 47.0 46.8 46.6 46.4
07279-023
LINEARITY ERROR (mV)
5 4 3 2 1 0 -1 -2
-40
-20 0 20 DRIVER OUTPUT CURRENT (mA)
40
60
0
1 2 3 4 VL PROGRAMMED VOLTAGE (V)
5
6
Figure 23. Driver Output Resistance vs. Output Current
Figure 26. HVOUT VL Linearity Error
Rev. 0 | Page 26 of 52
07279-026
46.2 -60
-3 -1
07279-025
-1.2 -2
07279-024
-1.5 -2
ADATE304
3 2 1
LINEARITY ERROR (mV)
1.0 RISE INPUT 0.8 RISE SHMOO
0
VOLTAGE (V)
-1 -2 -3 -4 -5 -6
07279-027
0.6
0.4
0.2
FALL SHMOO
5
6
7
8 9 10 11 12 VL PROGRAMMED VOLTAGE (V)
13
14
0
0.6
1.2 TIME (ns)
1.8
2.4
3.0
Figure 27. HVOUT VHH Linearity Error
80 70
Figure 30. Comparator Shmoo, 1.0 V Input, 0.7 ns (10% to 90%) Input, 50 Terminated
1.0 RISE INPUT
HVOUT DRIVER CURRENT (mA)
60 50
0.8 RISE SHMOO 0.6
40 30 20 10 0
07279-028
VOLTAGE (V)
0.4 FALL SHMOO 0.2 FALL INPUT
0
1
2 3 VHVOUT (V)
4
5
6
0
0.6
1.2 TIME (ns)
1.8
2.4
3.0
Figure 28. HVOUT VH Current Limit; VH = -0.1 V; VHVOUT Swept from -0.1 V to +6.0 V
80 60
Figure 31. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input, 50 Terminated
1.6 RISE INPUT 1.2
HVOUT DRIVER CURRENT (mA)
40 20 0 -20 -40 -60
VOLTAGE (V)
RISE SHMOO 0.8
0.4
FALL SHMOO
FALL INPUT
07279-029
5
6
7
8
9
11 VHVOUT (V)
10
12
13
14
15
0
0.6
1.2 1.8 TIME (ns)
2.4
3.0
Figure 29. HVOUT VHH Current Limit; VHH = 10.0 V; VHVOUT Swept from -5.9 V to +14.1 V
Figure 32. Comparator Shmoo, 1.5 V Input, 1.0 ns (10% to 90%) Input, 50 Terminated
Rev. 0 | Page 27 of 52
07279-032
-80
0
07279-031
-10 -1
0
07279-030
-7
0
FALL INPUT
ADATE304
10 0
TRAILING EDGE ERROR (ps) 0.6 0.4 0.2
LINEARITY ERROR (mV)
-10 -20 -30 -40 -50 1V NEG -60
07279-035
0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2 -1.4
1V POS
1
2
3 4 PULSEWIDTH (ns)
5
6
7
8 9 10
-1
0 1 2 3 4 5 PROGRAMMED THRESHOLD VOLTAGE (V)
6
7
Figure 33. Comparator Minimum Pulse Width, 1.0 V
100 DIFFERENTIAL COMPARATOR OFFSET (mV)
PROPAGATION DELAY VARIATION (ps)
Figure 36. Comparator Threshold Linearity
-2.5 -2.6 -2.7 -2.8 -2.9 -3.0 -3.1 -3.2 -2
75
TOTAL
50
25 RISING 0 FALLING -25
07279-036
1.0 1.5 2.0 INPUT SLEWRATE (10%-90%) (ns)
2.5
-1
0 1 2 3 INPUT COMMON-MODE VOLTAGE (V)
4
5
Figure 34. Comparator Slew Rate Dispersion, Input Swing = 1.5 V, Comparator Threshold = 0.75 V
1.8 1.6 1.4
LOAD CURRENT (mA)
Figure 37. Differential Comparator CMRR
15
10
1.2
VOLTAGE (V)
5
1.0 0.8 0.6 0.4 0.2 0 5 10 15 20 25 TIME (ns) 30 35 40 45 50
0
-5
-10
07279-037
-1
0
1
2 VDUTx (V)
3
4
5
6
Figure 35. Comparator Output Waveform, COMP_QH0P, COMP_QH0N
Figure 38. Active Load Commutation Response; VCOM = 2.0 V; IOH = IOL = 12 mA
Rev. 0 | Page 28 of 52
07279-040
0
-15 -2
07279-039
-50 0.5
07279-038
-70
-1.6 -2
ADATE304
6 6
4
LINEARITY ERROR (A)
5
2
IDUTx (nA)
07279-041
4
0
3
-2
2
-4
1
0
2
4 6 8 ACTIVE LOAD CURRENT (mA)
10
12
-1
0
1
2 3 VDUTx (V)
4
5
6
7
Figure 39. Active Load Current Linearity
0.8 0.6 0.4
LINEARITY ERROR (mV)
Figure 42. DUTx Pin Leakage in High-Z Mode
40 20 0 -20 -40 -60 -80 -100 -120 -40
0 -0.2 -0.4 -0.6 -0.8 -1.0 -1.2
07279-042
0
1
2 3 4 VCOM VOLTAGE (V)
5
6
7
-30
-20 -10 0 10 20 PMU OUTPUT CURRENT (mA)
30
40
Figure 40. Active Load VCOM Linearity
6.0
Figure 43. PMU Force Current Range A Linearity
0.8 0.6
LINEARITY ERROR (A)
5.5
0.4 0.2 0 -0.2 -0.4 -0.6 -2.0
5.0
IDUTx (nA)
4.5
4.0
3.5
07279-043
-1
0
1
2 3 VDUTx (V)
4
5
6
7
-1.5
-1.0 -0.5 0 0.5 1.0 PMU OUTPUT CURRENT (mA)
1.5
2.0
Figure 41. DUTx Pin Leakage in Low Leakage Mode
Figure 44. PMU Force Current Range B Linearity
Rev. 0 | Page 29 of 52
07279-046
3.0 -2
07279-045
-1.4 -1
LINEARITY ERROR (A)
0.2
07279-044
-6
0 -2
ADATE304
0.06
4 3
PMU VOLTAGE ERROR (mV)
07279-047
0.04
LINEARITY ERROR (A)
2 1 0 -1 -2 -3 -4 -40
0.02
0
-0.02
-0.04
-0.15
-0.10 -0.05 0 0.05 0.10 PMU OUTPUT CURRENT (mA)
0.15
0.20
-30
-20
-10
0 10 IDUTx (mA)
20
30
40
Figure 45. PMU Force Current Range C Linearity
0.006
Figure 48. PMU Force Voltage Range A Output Voltage Error at 6.75 V vs. Output Current
4 3
0.004
PMU VOLTAGE ERROR (mV)
LINEARITY ERROR (A)
2 1 0 -1 -2 -3
0.002
0
-0.002
-0.004
07279-048
0.015
0.020
-30
-20
-10
0 10 IDUTx (mA)
20
30
40
Figure 46. PMU Force Current Range D Linearity
Figure 49. PMU FV Range A Output Voltage Error at -1.25 V vs. Output Current
0.6
0.0006 0.0004
LINEARITY ERROR (A)
0.4
PMU VOLTAGE ERROR (mV)
0.0002 0 -0.0002 -0.0004 -0.0006 -0.0008 -0.0020 -0.0015 -0.0010 -0.0050 0 0.0050 0.0010 0.0015 0.0020 PMU OUTPUT CURRENT (mA)
0.2
0
-0.2
-0.4
07279-049
-1.5
-1.0
-0.5
0 0.5 IDUTx (mA)
1.0
1.5
2.0
Figure 47. PMU Force Current Range E Linearity
Figure 50. PMU FV Range B Output Voltage Error at 6.75 V vs. Output Current
Rev. 0 | Page 30 of 52
07279-052
-0.6 -2.0
07279-051
-0.006 -0.020 -0.015 -0.010 -0.005 0 0.005 0.010 PMU OUTPUT CURRENT (mA)
-4 -40
07279-050
-0.06 -0.20
ADATE304
0.6 0.7 0.6
PMU CURRENT ERROR (A)
07279-053
0.4
PMU VOLTAGE ERROR (mV)
0.5 0.4 0.3 0.2 0.1 0 -0.1 -2
0.2
0
-0.2
-0.4
-1.5
-1.0
-0.5
0 0.5 IDUTx (mA)
1.0
1.5
2.0
-1
0
1
2 3 VDUTx (V)
4
5
6
7
Figure 51. PMU FV Range B Output Voltage Error at -1.25 V vs. Output Current
5 0
PMU CURRENT ERROR (A)
Figure 54. PMU FI Range B Output Current Error at -2 mA vs. Output Voltage; Output Voltage Is Pulled Externally
0.7 0.6 0.5
-5 -10 -15 -20 -25
PMU CURRENT ERROR (A)
0.4 0.3 0.2 0.1 0 -0.1 -0.2
07279-054
-1
0
1
2 3 VDUTx (V)
4
5
6
7
-1
0
1
2 3 VDUTx (V)
4
5
6
7
Figure 52. PMU FI Range A Output Current Error at -32 mA vs. Output Voltage; Output Voltage Is Pulled Externally
10 0
Figure 55. PMU FI Range B Output Current Error at +2 mA vs. Output Voltage; Output Voltage Is Pulled Externally
0.0025 0.0020
-10
PMU CURRENT ERROR (A)
PMU CURRENT ERROR (A)
-20 -30 -40 -50 -60 -70 -80
07279-055
0.0015 0.0010 0.0005 0 -0.0005 -0.0010 -2
-1
0
1
2 3 VDUTx (V)
4
5
6
7
-1
0
1
2 3 VDUTx (V)
4
5
6
7
Figure 53. PMU FI Range A Output Current Error at +32 mA vs. Output Voltage; Output Voltage Is Pulled Externally
Figure 56. PMU FI Range E Output Current Error at -2 A vs. Output Voltage; Output Voltage Is Pulled Externally
Rev. 0 | Page 31 of 52
07279-058
-90 -2
07279-057
-30 -2
-0.3 -2
07279-056
-0.6 -2.0
ADATE304
0.0020
0.0015
PMU CURRENT ERROR (A)
0.0010
(100mV/DIV)
C1
0.0005
0
-1
0
1
2 3 VDUTx (V)
4
5
6
7
07279-059
-0.0005 -2
(500ps/DIV)
Figure 57. PMU FI Range E Output Current Error at +2 A vs. Output Voltage; Output Voltage Is Pulled Externally
0.5
Figure 60. Eye Diagram, 400 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
0.4
PMU VOLTAGE ERROR (mV)
0.3
(100mV/DIV)
C1
0.2
0.1
0
07279-063
07279-065
07279-060
-0.1 -2
-1
0
1 2 VDUTx (V)
3
4
5
(200ps/DIV)
Figure 58. PMU Measure Current Range B CMRR, Externally Pulling 1 mA, FVMI
Figure 61. Eye Diagram, 600 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
(100mV/DIV)
(200mV/DIV)
C1
C1
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(1ns/DIV)
(500ps/DIV)
Figure 59. Eye Diagram, 200 Mbps, PRBS31; VH = 1.0 V, VL = 0.0 V
Figure 62. Eye Diagram, 400 Mbps, PRBS31; VH = 2.0 V, VL = 0.0 V
Rev. 0 | Page 32 of 52
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ADATE304 SPI DETAILS
tCH
SCLK
tCSHA
CS
tCSSA
tCL tCSHD
tCSSD
tCSW tDH tDS
SDIN
DATA[15] DATA[14]
CH[1]
R/W
ADDR[1]
ADDR[0]
tDO
Figure 63. SPI Timing Diagram
Table 17. Serial Peripheral Interface Timing Requirements
Symbol tCH tCL tCSHA tCSSA tCSHD tCSSD tDH tDS tDO tCSW tCSTP Parameter SCLK minimum high SCLK minimum low CS assert hold CS assert setup CS deassert hold CS deassert setup SDIN hold SDIN setup SDOUT data out CS minimum between assertions 1 CS minimum directly after a read request Minimum delay after CS is deasserted before SCLK can be stopped (not shown in Figure 63); this allows any internal operations to complete Min 9.0 9.0 3.0 3.0 3.0 3.0 3.0 3.0 2 3 16 Max Unit ns ns ns ns ns ns ns ns ns SCLK cycles SCLK cycles SCLK cycles
15.0
1
An extra cycle is needed after a read request to prime the read data into the SPI shift register.
Rev. 0 | Page 33 of 52
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SDOUT
DO_15LAST
DO_14 LAST
DO_13 LAST
DO_12LAST
DO_2LAST
DO_1LAST
DO_0LAST
ADATE304
DEFINITION OF SPI WORD
The SPI can accept variable length words, depending on the operation. At most, the word length equals 24 bits: 16 bits of data, two channel selects, one read/write (R/W) selector, and a 5-bit address. Depending on the operation, the data can be smaller or, in the case of a read operation, nonexistent. Table 18. Channel Selection
Channel 1 0 0 1 1 Channel 0 0 1 0 1 Channel Selected NOP (no channel selected, no register changes) Channel 0 selected Channel 1 selected Channel 0 and Channel 1 selected
Table 19. R/W Definition
R/W 0 1 Description Current register specified by address shifts out of SDOUT on next shift operation Current data written to the register specified by address and channel select
Example 1: 16-Bit Write
Write 16 bits of data to a register or DAC; ignore unused MSBs. For example, Bit 15 and Bit 14 are ignored, and Bit 13 through Bit 0 are applied to the 14-bit DAC.
DATA[15:0] CH[1:0] R/W ADDR[4:0]
07279-068 07279-069 07279-072
07279-071
Figure 64. 16-Bit Write
Example 2: 14-Bit Write
Write 14 bits of data to the DAC.
DATA[13:0] CH[1:0] R/W ADDR[4:0]
Figure 65. 14-Bit Write
Example 3a: 2-Bit Write
Write two bits of data to the 2-bit register.
DATA[1:0] CH[1:0] R/W ADDR[4:0]
07279-070
Figure 66. 2-Bit Write
Example 3b: 2-Bit Write
Write two bits of data to the 2-bit register. Bit 15 through Bit 2 are ignored and Bit 1 through Bit 0 are applied to the register.
DATA[15:0]
CH[1:0]
R/W
ADDR[4:0]
Figure 67. 2-Bit Write
Example 4: Read Request
Read request and follow with a second instruction (could be NOP) to clock out the data.
CH[1:0] DATA[15:0] CH[1:0]
R/W = 0 R/W
ADDR[4:0] ADDR[4:0]
Figure 68. Read Request
Rev. 0 | Page 34 of 52
ADATE304
WRITE OPERATION
CS INPUT
SCLK INPUT
SDIN INPUT
DATA[15] DATA[14] DATA[13]
DATA[2] DATA[1] DATA[0]
CH[1]
CH[0]
R/W
ADDR[4]
ADDR[3]
ADDR[2]
ADDR[1]
ADDR[0]
X 24 25
0 SDOUT OUTPUT NOTES 1. R/W = 1. 2. X = DON'T CARE.
1
2
13
14
15
16
17
18 X
19
20
21
22
23
Figure 69. 16-Bit SPI Write
CS INPUT
SCLK INPUT
SDIN INPUT
DATA[1] DATA[0]
CH[1]
CH[0]
R/W
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
X
0 SDOUT OUTPUT NOTES 1. R/W = 1. 2. X = DON'T CARE.
1
2
3
4
5
6
7
8
9 X
10
11
Figure 70. 2-Bit SPI Write
Rev. 0 | Page 35 of 52
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07279-073
ADATE304
READ OPERATION
The read operation is a two-stage operation. First, a word is shifted in, specifying which register to read. CS is deasserted for three clock cycles, and then a second word is shifted in to obtain the readback data. This second word can be either another operation or an NOP address. If another operation is shifted in, it must shift in at least eight bits of data to read back the previous specified data. The NOP address can be used for this read if there is no need to read/write another register. To maintain the clarity of the operation, it is strongly recommended that the NOP address be used for all reads. Any register read that is fewer than 16 bits has zeros filled in the top bits to make it a 16-bit word.
CS INPUT SCLK INPUT
SDIN INPUT SDOUT OUTPUT NOTES 1. X = DON'T CARE.
READ INSTRUCTION
X
NOP
X
X
READ DATA
X
07279-075
Figure 71. SPI Read Overview
CS INPUT SCLK INPUT
SDIN INPUT 0 SDOUT OUTPUT NOTES 1. X = DON'T CARE.
DATA[15:0], VALUE IS A DON'T CARE 1 2 13 14 15
CH[1]
CH[0]
R/W
ADDR[4] ADDR[3] ADDR[2] ADDR[1] ADDR[0]
X 24 25
16
17 X
18
19
20
21
22
23
Figure 72. SPI Read--Details of Read Request
CS INPUT SCLK INPUT
SDIN INPUT 0 SDOUT OUTPUT
DATA[15:0], VALUE IS A DON'T CARE 1 2 13
RDATA[2]
CH[1]
CH[0]
R/W = 1
ADDR[4:0] = 0x00 (NOP) 19 20 21 X 22 23 24
X 25
14
RDATA[1]
15
RDATA[0]
16
17
18
RDATA[15] RDATA[14]
Figure 73. SPI Read--Details of Read Out
Rev. 0 | Page 36 of 52
07279-077
NOTES 1. RDATA IS THE REGISTER VALUE BEING READ. 2. X = DON'T CARE.
07279-076
ADATE304
RESET OPERATION
The ADATE304 contains an asynchronous reset feature. The ADATE304 can be reset to the default values shown in Table 20
100ns MINIMUM RST
by utilizing the RST pin. To initiate the reset operation, deassert the RST pin for a minimum of 100 ns and deassert the CS pin for a minimum of two SCLK cycles.
CS
MINIMUM OF TWO SCLK EDGES AFTER ASSERTING RST BEFORE RESUMING NORMAL OPERATION.
Figure 74. Reset Operation
Rev. 0 | Page 37 of 52
07279-078
SCLK
ADATE304 REGISTER MAP
The ADDR[4:0] bits determine the destination register of the data being written to the ADATE304. Table 20. Register Selection
DATA[15:0] N/A 1 DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[13:0] DATA[15:0] DATA[2:0] DATA[2:0] DATA[9:0] DATA[2:0] DATA[0] DATA[1:0] DATA[1:0] DATA[2:0] N/A
1
CH[1:0] N/A CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1] CH[0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] CH[1:0] N/A
R/W N/A R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R N/A
ADDR[4:0] 0x00 0x01 0x02 0x03 0x04 0x05 0x06 0x07 0x08 0x09 0x0A 0x0A 0x0B 0x0C 0x0D 0x0E 0x0F 0x10 0x11 0x12 0x13 0x14 to 0x1F
Register Selected NOP VH DAC level VL DAC level VT/VCOM DAC level VOL DAC level VOH DAC level VCH DAC level VCL DAC level V(IOH ) DAC level V(IOL ) DAC level OVD high level OVD low level PMUDAC level PE/PMU enable Channel state PMU state PMU measure enable Differential comparator enable 16-bit DAC monitor OVD_CHx alarm mask OVD_CHx alarm state Reserved
Reset State N/A 4096d 4096d 4096d 4096d 4096d 4096d 4096d 4096d 4096d 4096d 4096d 16384d 000b 000b 0d 000b 0b 00b 01b N/A N/A
N/A means not applicable.
Rev. 0 | Page 38 of 52
ADATE304 DETAILS OF REGISTERS
Table 21. PE/PMU Enable (ADDR[4:0] = 0x0C)
Bit DATA[2] Name PMU enable Description 0 = disable PMU force output and clamps, place PMU in MV mode 1 = enable PMU force output When set to 0, the PMU state bits are ignored, except for the PMU sense path (DATA[7]) 0 = normal driver operation 1 = force driver to VT See Table 29 for complete functionality of this bit 0 = enable driver functions 1 = disable driver (low leakage) See Table 29 for complete functionality of this bit
DATA[1]
Force VT
DATA[0]
PE disable
Table 22. Channel State (ADDR[4:0] = 0x0D)
Bit DATA[2] Name HV mode select Description 0 = HV driver in low impedance. 1 = enable HV driver. This bit affects Channel 0 only. Ensure that the Channel 0 bit in SPI write is active. Channel 1 bit in SPI write is don't care. 0 = disable load. 1 = enable load. See Table 29 for complete functionality of this bit. 0 = enable Driver high-Z function. 1 = enable Driver VTERM function. See Table 29 for complete functionality of this bit.
DATA[1]
Load enable
DATA[0]
Driver high-Z or VT
Table 23. PMU State (ADDR[4:0] = 0x0E) 1, 2
Bit DATA[9:8] Name PMU input selection Description 00 = VDUTGND (calibrated for 0.0 V voltage reference) 01 = 2.5 V + VDUTGND (calibrated for 0.0 A current reference) 1X = PMUDAC 0 = internal sense 1 = external sense 0 = disable clamps 1 = enable clamps 0 = measure voltage mode 1 = measure current mode 0 = force voltage mode 1 = force current mode 0XX = 2 A range 100 = 20 A range 101 = 200 A range 110 = 2 mA range 111 = 32 mA range
DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0]
PMU sense path Reserved PMU clamp enable PMU measure voltage or current PMU force voltage or current PMU range
1
2
Note that when ADDR[4:0] = 0x0C, the PMU enable bit (DATA[2]) = 0, PMU force outputs and clamps are disabled, and the PMU is placed into measure voltage mode. PMU State DATA[9:8] and DATA[6:0] are ignored, and only the DATA[7] PMU sense path is valid. X means don't care.
Rev. 0 | Page 39 of 52
ADATE304
Table 24. PMU Measure Enable (ADDR[4:0] = 0x0F) 1
Bit DATA[2:1] Name MEASOUT01 select Description 00 = PMU MEASOUT Channel 0 01 = PMU MEASOUT Channel 1 10 = Temperature sensor ground reference 11 = Temperature sensor 0 = MEASOUT01 is tristated 1 = MEASOUT01 is enabled
DATA[0]
1
MEASOUT01 output enable
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 25. Differential Comparator Enable (ADDR[4:0] = 0x10) 1
Bit DATA[0] Name Differential Comparator Enable Description 0 = differential comparator is disabled; the Channel 0 normal window comparator (NWC) outputs are located on Channel 0 1 = differential comparator is enabled; the differential comparator outputs are located on Channel 0
1
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 26. DAC16_MON (16-Bit DAC Monitor) (ADDR[4:0] = 0x11) 1
Bit DATA[1] DATA[0] Name 16-Bit DAC mux enable 16-Bit DAC mux select Description 0 = 16-bit DAC mux is tristated 1 = 16-bit DAC mux is enabled 0 = 16-bit DAC Channel 0 1 = 16-bit DAC Channel 1
1
This register is written to or read from when either of the CH[1:0] bits is 1.
Table 27. OVD_CHx Alarm Mask (ADDR[4:0] = 0x12)
Bit DATA[1] DATA[0] Name PMU mask OVD mask Description 0 = disable PMU alarm flag 1 = enable PMU alarm flag 0 = disable OVD alarm flag 1 = enable OVD alarm flag
Table 28. OVD_CHx Alarm State (ADDR[4:0] = 0x13) 1
Bit DATA[2] DATA[1] DATA[0] Name PMU clamp flag OVD high flag OVD low flag Description 0 = PMU is not clamped 1 = PMU is clamped 0 = DUT voltage < OVD high voltage 1 = DUT voltage > OVD high voltage 0 = DUT voltage > OVD low voltage 1 = DUT voltage < OVD low voltage
1
This register is a read-only register.
Rev. 0 | Page 40 of 52
ADATE304 USER INFORMATION
POWER SUPPLY CONSIDERATIONS
Power Supply Sequencing
It is recommended that the power supplies be brought up in the following order: 1. 2. 3. 4. 5. Grounds (DGND, AGND, VREF_GND) VSS VCC, VCOMP_VTT, and VREF VDD VPLUS
Power Supply Decoupling
The ADATE304 is a high performance device that requires close attention to power supply decoupling to deliver the best performance. The use of full power planes with low inductance capacitors placed as close to the power pins as possible is recommended. The following power connections are the most important: * * * * VPLUS to AGND (for the HVOUT driver) VDD to VSS near the DUTx pin (for the driver) VDD and VSS to AGND near the DUTx pin (for the comparators) VCC to DGND (for the digital)
If the HVOUT pin is not used, the VPLUS supply can be connected to VDD.
Additionally, large bulk capacitors (that is, 10 F) should be used on every power supply on the printed circuit board (PCB).
TRUTH TABLES
Table 29. Driver and Load Truth Table 1
PE Disable DATA[0] ADDR[4:0] = 0x0C 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
1
Registers Force VT Load Enable DATA[1] DATA[1] ADDR[4:0] = 0x0C ADDR[4:0] = 0x0D X X 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 X 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
Signals Driver High-Z/VT DATA[0] ADDR[4:0] = 0x0D X X 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
DATAx X X 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
RCVx X X 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Driver State High-Z without clamps VT VL High-Z with clamps VH High-Z with clamps VL VT VH VT VL High-Z with clamps VH High-Z with clamps VL High-Z with clamps VH High-Z with clamps
Load State Power-down Power-down Power-down Power-down Power-down Power-down Power-down Power-down Power-down Power-down Active off Active on Active off Active on Active on Active on Active on Active on
X means don't care.
Table 30. HVOUT Truth Table 1
HVOUT Mode Select DATA[2] ADDR[4:0] =0x0D 1 1 1 0
1
Channel 0 RCV 1 0 0 X
Channel 0 DATA X 0 1 X
HVOUT Driver Output VHH mode; VHH = (VT + 1 V) x 2 + DUTGND (Channel 0 VT DAC) VL (Channel 0 VL DAC) VH (Channel 0 VH DAC) Disabled (HVOUT pin set to 0 V low impedance)
X means don't care.
Rev. 0 | Page 41 of 52
ADATE304
Table 31. Comparator Truth Table
Differential Comparator Enable DATA[0] ADDR[4:0] = 0x10 0
1
COMP_QH0 Normal window mode Logic high: VOH0 < VDUT0 Logic low: VOH0 > VDUT0 Differential comparator mode Logic high: VOH0 < VDUT0 - VDUT1 Logic low: VOH0 > VDUT0 - VDUT1
COMP_QL0 Normal window mode Logic high: VOL0 < VDUT0 Logic low: VOL0 > VDUT0 Differential comparator mode Logic high: VOL0 < VDUT0 - VDUT1 Logic low: VOL0 > VDUT0 - VDUT1
COMP_QH1 Normal window mode Logic high: VOH1 < VDUT1 Logic low: VOH1 > VDUT1 Normal window mode Logic high: VOH1 < VDUT1 Logic low: VOH1 > VDUT1
COMP_QL1 Normal window mode Logic high: VOL1 < VDUT1 Logic low: VOL1 > VDUT1 Normal window mode Logic high: VOL1 < VDUT1 Logic low: VOL1 > VDUT1
Rev. 0 | Page 42 of 52
ADATE304
DETAILS OF DACS vs. LEVELS
There are ten 14-bit DACs per channel. These DACs provide levels for the driver, comparator, load currents, VHH buffer, OVD, and clamp levels. There are three versions of output levels as follows: * -2.5 V to +7.5 V and tracks DUTGND. Controls the VH, VL, VT/VCOM/VHH, VOH, VOL, VCH, and VCL levels. * * -3.0 V to +7.0 V and tracks DUTGND. Controls the OVD levels. -2.5 V to +7.5 V and does not track DUTGND. Controls the IOH and IOL levels.
There is one 16-bit DAC per channel. This DAC provides the levels for the PMU. The output level is as follows: * -2.5 V to +7.5 V and tracks DUTGND; controls the PMU levels.
Programmable Range 1 (All 0s to All 1s) -2.5 V to +7.5 V -3.0 V to +17.0 V -3.0 V to +7.0 V -6 mA to +18 mA -2.5 V to +7.5 V -50 mA to +50 mA -4 mA to +4 mA -400 A to +400 A -40 A to +40 A -4 A to +4 A
Table 32. Level Transfer Functions
DAC Transfer Function VOUT = 2.0 x (VREF - VREF_GND) x (Code/(214)) - 0.5 x (VREF - VREF_GND) + VDUTGND Code = [VOUT - VDUTGND + 0.5 x (VREF - VREF_GND)] x [(214)/(2.0 x (VREF - VREF_GND))] VOUT = 4.0 x (VREF - VREF_GND) x (Code/(214)) - 1.0 x (VREF - VREF_GND) + 2.0 + VDUTGND Code = [VOUT - VDUTGND - 2.0 + 1.0 x (VREF - VREF_GND)] x [(214)/(4.0 x (VREF - VREF_GND))] VOUT = 2.0 x (VREF - VREF_GND) x (Code/(214)) - 0.6 x (VREF - VREF_GND) + VDUTGND Code = [VOUT - VDUTGND + 0.6 x (VREF - VREF_GND)] x [(214)/(2.0 x (VREF - VREF_GND))] IOUT = [2.0 x (VREF - VREF_GND) x (Code/(214)) - 0.5 x (VREF - VREF_GND)] x (0.012/5.0) Code = [(IOUT x (5.0/0.012)) + 0.5 x (VREF - VREF_GND)] x [(214)/(2.0 x (VREF - VREF_GND))] VOUT = 2.0 x (VREF - VREF_GND) x (Code/(216)) - 0.5 x (VREF - VREF_GND) + VDUTGND Code = [VOUT - VDUTGND + 0.5 x (VREF - VREF_GND)] x [(216)/(2.0 x (VREF - VREF_GND))] IOUT = [2.0 x (VREF - VREF_GND) x (Code/(216)) - 0.5 x (VREF - VREF_GND) - 2.5] x (0.050/5.0) Code = [(IOUT x (5.0/0.050)) + 2.5 + 0.5 x (VREF - VREF_GND)] x [(216)/(2.0 x (VREF - VREF_GND))] IOUT = [2.0 x (VREF - VREF_GND) x (Code/(216)) - 0.5 x (VREF - VREF_GND) - 2.5] x (0.004/5.0) Code = [(IOUT x (5.0/0.004)) + 2.5 + 0.5 x (VREF - VREF_GND)] x [(216)/(2.0 x (VREF - VREF_GND))] IOUT = [2.0 x (VREF - VREF_GND) x (Code/(216)) - 0.5 x (VREF - VREF_GND) - 2.5] x (0.0004/5.0) Code = [(IOUT x (5.0/0.0004)) + 2.5 + 0.5 x (VREF - VREF_GND)] x [(216)/(2.0 x (VREF - VREF_GND))] IOUT = [2.0 x (VREF - VREF_GND) x (Code/(216)) - 0.5 x (VREF - VREF_GND) - 2.5] x (0.00004/5.0) Code = [(IOUT x (5.0/0.00004)) + 2.5 + 0.5 x (VREF - VREF_GND)] x [(216)/(2.0 x (VREF - VREF_GND))] IOUT = [2.0 x (VREF - VREF_GND) x (Code/(216)) - 0.5 x (VREF - VREF_GND) - 2.5] x (0.000004/5.0) Code = [(IOUT x (5.0/0.000004)) + 2.5 + 0.5 x (VREF - VREF_GND)] x [(216)/(2.0 x (VREF - VREF_GND))]
1
Levels VH, VL, VT/VCOM, VOL, VOH, VCH, VCL VHH OVD IOH, IOL PMUDAC PMUDAC (PMU FI Range A) PMUDAC (PMU FI Range B) PMUDAC (PMU FI Range C) PMUDAC (PMU FI Range D) PMUDAC (PMU FI Range E)
Programmable range includes a margin outside the specified part performance, allowing for offset/gain calibration.
Table 33. Load Transfer Functions
Load Level IOL IOH
1
Transfer Function 1 V(IOL)/5 V x 12 mA V(IOH)/5 V x 12 mA
V(IOH)and V(IOL) DAC levels are not referenced to DUTGND.
Table 34. PMU Transfer Functions
PMU Mode Force Voltage Measure Voltage Force Current Measure Current
1
Transfer Functions VOUT = PMUDAC VMEASOUT01 = VDUTx (internal sense) or VMEASOUT01 = VPMUS_CHx (external sense) IOUT = [PMUDAC - (VREF/2)]/(R 1 x 5) VMEASOUT01 = (VREF/2) + VDUTGND + (IDUTx x 5 x R1)
R = 15.5 for Range A; 250 for Range B; 2.5 k for Range C; 25 k for Range D; 250 k for Range E.
Table 35. PMU User Required Capacitors
Capacitor 220 pF 220 pF 330 pF 330 pF Location Across Pin C10 (FFCAP_0B) and Pin E10 (FFCAP_0A) Across Pin C1 (FFCAP _1B) and Pin E1 (FFCAP_1A) Between GND and Pin B9 (SCAP0) Between GND and Pin B2 (SCAP1)
Rev. 0 | Page 43 of 52
ADATE304
Table 36. Temperature Sensor
Temperature 0K 300 K xK Output 0V 3V (x K) x 10 mV/K
Table 37. Power Supply Ranges
Parameter Nominal VDD Nominal VSS Driver VH range VL range VT range Functional Amplitude Reflection Clamp VCH Range VCL Range Comparator Input Voltage Range Active Load VCOM Range PMU Force Voltage Range Measure Voltage Range Force Current Voltage Range Measure Current Voltage Range Low Clamp Range High Clamp Range OVD Range 1 +10.75 V -5.00 V -1.15 V to +6.75 V -1.25 V to +6.65 V -1.25 V to +6.75 V 8.0 V -1.0 V to +6.75 V -1.25 V to +5.75 V -1.25 V to +6.75 V -1.00 V to +6.50 V -1.25 V to +6.75 V -1.25 V to +6.75 V -1.25 V to +6.75 V -1.25 V to +6.75 V -1.25 V to +4.75 V 0.75 V to 6.75 V -2.25 V to +7.0 V Range 2 +10.0 V -5.75 V -1.9 V to +6.0 V -2.0 V to +5.9 V -2.0 V to +6.0 V 8.0 V -1.0 V to +6.0 V -2.0 V to +5.0 V -2.0 V to +6.0 V -1.75 V to +5.75 V -2.0 V to +6.0 V -2.0 V to +6.0 V -2.0 V to +6.0 V -2.0 V to +6.0 V -2.0 V to +4.0 V 0.0 V to 6.0 V -3.0 V to +7.0 V
Table 38. Default Test Conditions (Range 1)
Name VH DAC Level VL DAC Level VT/VCOM DAC Level VOL DAC Level VOH DAC Level VCH DAC Level VCL DAC Level IOH DAC Level IOL DAC Level OVD Low DAC Level OVD High DAC Level PMUDAC DAC Level PE/PMU Enable Channel State PMU State PMU Measure Enable Differential Comparator Enable 16-Bit DAC Monitor OVD_CHx Alarm Mask Data Input Receive Input DUTx Pin Comparator Output Default Test Condition +2.0 V +0.0 V +1.0 V -1.0 V +6.0 V +7.5 V -2.5 V 0.0 A 0.0 A -2.5 V +6.5 V 0.0 V 0x0000: PMU disabled, VT not forced through driver, PE enabled 0x0000: HV mode disabled, load disabled, VTERM inactive 0x0000: input of DUTGND, internal sense, clamps disabled, FVMV, Range E 0x0000: MEASOUT01 pin tristated 0x0000: normal window comparator mode 0x0000: DAC16_MON tristated 0x0000: disable alarm functions Logic low Logic low Unterminated Unterminated
Rev. 0 | Page 44 of 52
ADATE304
RECOMMENDED PMU MODE SWITCHING SEQUENCES
To minimize any possible aberrations and voltage spikes on the DUT output, specific mode switching sequences are recommended for the following transitions: * * * PMU disable to PMU enable. PMU force voltage mode to PMU force current mode. PMU force current mode to PMU force voltage mode.
PMU Force Voltage Mode to PMU Force Current Mode
Step 1. Table 42 lists the state of registers in force voltage mode. Table 42.
Register PE/PMU Enable Register, ADDR[4:0] = 0x0C PMU State Register, ADDR[4:0] = 0x0E Bits DATA[2] Setting 1
PMU Disable to PMU Enable
Note that, in Table 39 through Table 49, X indicates the don't care bit. Step 1. Table 39 lists the state of the registers in PMU disabled mode. Table 39.
Register PE/PMU Enable Register, ADDR[4:0] = 0x0C PMU State Register, ADDR[4:0] = 0x0E Bits DATA[2] Setting 0
DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0]
XX X X X X 0 XXX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 43). Table 43.
Register PMU State Register, ADDR[4:0] = 0x0E Bits DATA[9:8] Setting 01 Comments Set 2.5 V + DUTGND input selection
DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0]
XX X X X X X XXX
DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0]
X X X X 1 0XX
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 40). Table 40.
Register PMU State Register, ADDR[4:0] = 0x0E Bits DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] Setting 1X or 00 X X X X 0 Comments Set desired input selection
Set to force current mode The 2 A range has the minimum offset current
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 44). Table 44.
Register VIN 16-Bit DAC, ADDR[4:0] = 0x0B Bits DATA[15:0] Setting X Comments Update the VIN 16-Bit DAC register to the desired value
DATA[2:0]
XXX
This bit must be set to force voltage mode to reduce aberrations Set desired range
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 45). Table 45.
Register PMU State Register, ADDR[4:0] = 0x0E Bits DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0] Setting 1X X X X X 1 XXX Comments Set VIN input selection
Step 3. Write to Register ADDR[4:0] = 0x0C (see Table 41). Table 41.
Register PE/PMU Enable Register, ADDR[4:0] = 0x0C Bits DATA[2] Setting 1 Comments PMU is now enabled in force voltage mode
Set to the desired current range
Rev. 0 | Page 45 of 52
ADATE304
Transition from PMU Force Current Mode to PMU Force Voltage Mode
Step 1. Table 46 lists the state of the registers in force current mode. Table 46.
Register PE/PMU Enable Register, ADDR[4:0] = 0x0C PMU State Register, ADDR[4:0] = 0x0E Bits DATA[2] DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0] Setting 1 XX X X X X 1 XXX
Step 3. Write to Register ADDR[4:0] = 0x0B (see Table 48). Table 48.
Register VIN 16-Bit DAC, ADDR[4:0] = 0x0B Bits DATA[15:0] Setting X Comments Update the VIN 16-Bit DAC register to the desired value
Step 4. Write to Register ADDR[4:0] = 0x0E (see Table 49). Table 49.
Register PMU State Register, ADDR[4:0] = 0x0E Bits DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0] Setting 1X X X X X 0 XXX Comments Set VIN input selection
Step 2. Write to Register ADDR[4:0] = 0x0E (see Table 47). Table 47.
Register PMU State Register, ADDR[4:0] = 0x0E Bits DATA[9:8] DATA[7] DATA[6] DATA[5] DATA[4] DATA[3] DATA[2:0] Setting 00 X X X X 0 XXX Comments Set DUTGND input selection
Force voltage mode
Set to force voltage mode Set to the desired current range
Rev. 0 | Page 46 of 52
ADATE304 BLOCK DIAGRAMS
VCL VH VL DATA DRIVER VCH PE DISABLE DATA[0] (ADDR[4:0] = 0x0C) FORCES SWITCH OPEN WHEN 1 ROUT = 47 (TRIMMED) DUT
VT
DRIVER HIGH-Z/VT DATA[0] (ADDR[4:0] = 0x0D) VT BUFFER WHEN 1 HIGH-Z BUFFER WHEN 0 RCV
V(IOH)
VCOM
FORCE VT DATA[1] (ADDR[4:0] = 0x0C) OVERRIDES THE RCV PIN AND FORCES VTERM MODE ON THE DRIVER AND LOAD POWER-DOWN MODE
V(IOL)
07279-079 07279-080
LOAD ENABLE DATA[1] (ADDR[4:0] = 0x0D) FORCES SWITCHES OPEN AND POWERS DOWN LOAD WHEN 0
Figure 75. Driver and Load Block Diagram
VHH = (VT + 1V) x 2 + DUTGND
~5 HVOUT
VH VL DATA RCV (SHOWN IN RCV = 0 STATE)
48
HV MODE SELECT DATA[2] (ADDR [4:0] = 0x0D) DISABLES HV DRIVER AND FORCES 0V ON HVOUT WHEN 0
Figure 76. HVOUT Driver Output Stage
Rev. 0 | Page 47 of 52
ADATE304
VOH0 DUT0 - VOH NWC + + VOL NWC - - VOH DMC + 2:1 COMP_QH0 MUX DIFFERENTIAL COMPARATOR ENABLE DATA[0] (ADDR[4:0] = 0x10) 2:1 COMP_QL0 MUX
VOL0 VOH0
DUT1
DU T0 - DUT0- DU T1 DUT1
DIFFERENTIAL BUFFER VOL0
+ VOL DMC -
07279-081
NOTES 1. DIFFERENTIAL COMPARATOR ONLY ON CHANNEL 0.
Figure 77. Comparator Block Diagram
COMPARATOR OUTPUT (AB)
VTT = 3.3V
RECEIVER
OUT HIGH = 1.55V 100 OUT CM = 1.42V OUT LOW = 1.30V 50 50
GND
Figure 78. Comparator Output Scheme
Rev. 0 | Page 48 of 52
07279-082
ADATE304
PMU MEASURE V/I DATA[4] (ADDR[4:0] = 0x0E) PMU SENSE PATH DATA[7] (ADDR[4:0] = 0x0E)
MEASURE V MEASURE I MEASOUT01 SELECT DATA[2:1] (ADDR[4:0] = 0x0F) MUX PMU FORCE V/I DATA[3] (ADDR[4:0] = 0x0E) MEASURE OUT CH[1] PMU V/I TEMP SENSE GND REF TEMP SENSE MUX MEASOUT01 OUTPUT ENABLE DATA[0] (ADDR[4:0] = 0x0F) ONE PER DEVICE MUX MUX
EXTERNAL DUT SENSE PIN
IN-AMP G = 5
10k
REF
2.5 + DUTGND
225k 2A 20A
22.5k 200A
2.25k 2mA
250 DUTx
15.5
PMU INPUT SELECTION DATA[9:8] (ADDR[4:0] = 0x0E)
MV VIN 2.5V + DUTGND DUTGND MUX PMU CLAMP ENABLE DATA[5] (ADDR[4:0] = 0x0E) VCH 330pF SCAPx (EXTERNAL) 32mA BUFFER
FFCAP_xA
FFCAP_xB CRA = 220pF
MEASURE V (AT OUTPUT OF SENSE MUX)
VCL
32mA
Figure 79. PMU Block Diagram
Rev. 0 | Page 49 of 52
07279-083
NOTES 1. SWITCHES CONNECTED WITH DOTTED LINES REPRESENT PMU RANGE DATA[2:0] (ADDR[4:0] = 0x0E); WHEN PMU ENABLE D ATA[2] = 0 (ADDR[4:0] = 0x0C), ALL SWITCHES OPEN AND PMU POWERS DOWN. 2. THE EXTERNAL SENSE PATH MUST CLOSE THE LOOP TO ENABLE THE CLAMPS TO OPERATE CORRECTLY. 3. 32mA RANGE HAS ITS OWN OUTPUT BUFFER. 4. 32mA BUFFER TRISTATES WHEN NOT IN USE.
ADATE304
(ADDR[4:0] = 0x12) DATA[0] OVD MASK ENABLES OVD FLAGS TO ALARM OVD_CHx PIN 6.5V 1 OVD HIGH LEVEL DAC (ADDR[4:0] = 0x0A, CH[1]) OVD_CHx SHORT-CIRCUIT CURRENT = 100A DUT
ADATE304
-2.5V 1 OVD LOW LEVEL DAC (ADDR[4:0] = 0x0A, CH[0])
PMU V/I CLAMP FLAG
(ADDR[4:0] = 0x12) DATA[1] PMU MASK ENABLES PMU V/I FLAG TO ALARM OVD_CHx PIN
(ADDR[4:0] = 0x13) 2 DATA[2] DATA[1] DATA[0]
1THE
Figure 80. OVD Block Diagram
Rev. 0 | Page 50 of 52
07279-084
OVD HIGH/LOW LEVEL DAC IS SHARED BY EACH CHANNEL; THEREFORE, ONLY ONE OVD HIGH/LOW VOLTAGE LEVEL CAN BE SET PER CHIP. THE OVD DACs PROVIDE A VOLTAGE RANGE OF -3V TO +7V. THE RECOMMENDED HIGH/LOW SETTINGS ARE +6.5V/-2.5V. (THESE VALUES NEED TO BE PROGRAMMED BY THE USER UPON STARTUP/RESET.) 2THIS IS A READ ONLY REGISTER THAT ALLOWS THE USER TO DETERMINE THE CAUSE OF THE ACTIVE OVD FLAG.
ADATE304 OUTLINE DIMENSIONS
A1 BALL CORNER 9.10 9.00 SQ 8.90 A1 BALL CORNER
10 9 8 7 6 5 4 3 2 1 A B C
6.731 REF SQ
7.20 BSC SQ 0.80 BSC
D E F G H J K
TOP VIEW
0.90 REF
BOTTOM VIEW 0.305 REF
*1.20 1.09 1.00
DETAIL A
DETAIL A
0.36 REF
0.83 0.76 0.69
0.38 0.33 0.28 SEATING PLANE
0.53 0.48 0.43 BALL DIAMETER
COPLANARITY 0.12
Figure 81. 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA] (BC-84-2) Dimensions shown in millimeters
ORDERING GUIDE
Model ADATE304BBCZ 1
1
Temperature Range -40C to +85C
Package Description 84-Ball Chip Scale Package Ball Grid Array [CSP_BGA]
Package Option BC-84-2
Z = RoHS Compliant Part.
Rev. 0 | Page 51 of 52
091108-A
*COMPLIANT TO JEDEC STANDARDS MO-219 WITH EXCEPTION TO PACKAGE HEIGHT.
ADATE304 NOTES
(c)2008 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D07279-0-10/08(0)
Rev. 0 | Page 52 of 52

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